Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material

• US 6,413,852 B1
• Filed: 08/31/2000
• Issued: 07/02/2002
• Est. Priority Date: 08/31/2000
• Status: Expired due to Term

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Jahnes, Christopher Vincent, Purushothaman, Sampath, Petrarca, Kevin S., Grill, Alfred, Whitehair, Stanley Joseph, Nitta, Satyanarayana Venkata, Saenger, Katherine Lynn, Hedrick, Jeffrey Curtis
• Primary Examiner(s): Fabanny, Jr., Wael
• Assistant Examiner(s): Brewster, William M.
• Application Number:
  US09/652,754
• Time in Patent Office: 670 Days
• Field of Search: 438/618, 438/619, 438/622, 257/276
• US Class Current: 438/619
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

Abstract

A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics. The inventive method includes the steps of: (a) forming a first planar via plus line level pair embedded in a dielectric matrix formed from one or more solid dielectrics and comprising a via level dielectric and a line level dielectric on a substrate, wherein, at least one of said solid dielectrics is at least partially sacrificial; (b) etching back sacrificial portions of said at least partially sacrificial dielectrics are removed to leave cavities extending into and through said via level, while leaving, at least some of the original via level dielectric as a permanent dielectric under said lines; (c) partially filling or overfilling said cavities with a place-holder material which may or may not be sacrificial; (d) planarizing the structure by removing overfill of said place-holder material; (e) repeating, as necessary, steps (a)-(d); (f) forming a dielectric bridge layer over the planar structure; and (g) forming air gaps by at least partially extracting said place-holder material.

Claims

1. A method for forming a multilayer interconnect structure on a substrate, said structure comprising interconnected conductive wiring and vias spaced apart by a combination of solid and gaseous dielectrics, said method comprising the steps of:

(a) forming on a substrate a first planar via plus line level pair embedded in a dielectric matrix formed from one or more solid dielectrics and comprising a via level dielectric and a line level dielectric, wherein at least one of said solid dielectrics is at least partially sacrificial;

(b) etching back sacrificial portions of said at least partially sacrificial dielectrics to form cavities extending into and through said via level, while leaving at least some of the original via level dielectric as a permanent dielectric under said lines;

(c) at least partially filling and then overfilling said cavities with a place-holder material which may or may not be sacrificial;

(d) planarizing the structure by removing overfill of said place-holder material;

(e) repeating, as necessary, steps (a)-(d);

(f) forming a dielectric bridge layer over the planar structure; and

(g) forming air gaps by at least partially extracting said place-holder material.

2. The method of claim 1 wherein the step of forming a first planar via plus line level pair embedded in a dielectric matrix comprising one or more solid dielectrics comprises the steps of:

forming dielectric layers whose combined thickness approximates the sum of the desired line thickness and the desired via thickness;

forming dual relief cavities corresponding to line and via patterns;

blanket depositing one or more thin layers of conductive liner and/or barrier materials and overfilling with a low resistivity material; and

planarizing said conductive and low resistivity material, stopping on the dielectric'"'"'s top surface.

3. The method of claim 1 further including the step of forming on said substrate a planar “

line level”

comprising conductive lines embedded in a dielectric matrix, said dielectric matrix comprising (i) one or more permanent dielectrics (ii) one or more permanent dielectrics that will be at least partially removed, (iii) a place-holder material that is extracted at a later time, or any combination thereof.

4. The method of claim 1 further including the step of forming perforations or holes in said bridge layer before extracting said place-holder material that is extracted at a later time.

5. The method of claim 4 further including the step of sealing said perforations or holes in said bridge layer with a pinch-off dielectric material after said extraction process, said pinch-off dielectric being the same or different from the material of the dielectric bridge layer.

6. The method of claim 1 wherein the place-holder material is a low-k dielectric that is left in the structure.

7. The method of claim 1 wherein the place-holder material is a low-k dielectric that is left in the structure, and the etchback process is modified to form cavities in the via level dielectric that do not extend through the entire thickness of said via level.

8. The method of claim 1 wherein the sacrificial portions of the at least partially sacrificial dielectrics are removed by the step of anisotropically etching the dielectrics, using the conductive wiring structures as a mask.

9. The method of claim 1 further including forming sidewall spacers on at least some of the interconnect structure'"'"'s conductive line and/or via features.

10. The method of claim 9 wherein said sidewall spacers are formed by:

lining the sides and bottom of a cavity formed by removing said sacrificial material with a layer of sidewall spacer material; and

anisotropically etching sidewall spacer material to remove it from the bottom of the cavity while leaving it on the sides.

11. The method of claim 9 wherein said sidewall spacers are formed of a permanent dielectric material protected during the permanent-dielectric etchback by a mask whose dimensions slightly exceed the dimensions of the conductive wiring features.

12. The method of claim 11 wherein said mask is formed in a self-aligned electroless metal deposition step which deposits material only on top of the conductive wiring features.

13. The method of claim 1 wherein the step of forming a dielectric matrix includes the steps of:

forming a layer of a barrier dielectric as the first (bottom) layer of the dielectric matrix; and

forming holes or perforations in the barrier dielectric before or after applying the additional layers of the dielectric matrix.

14. The method of claim 1 further including the step of selecting materials of said conductive wiring and via from the group of metals including Al, Cu, Au, Ag, W, Ta, Pd, Al—

Cu, Cu—

Al, Cu—

In, Cu—

Sn, Cu—

Mg, Cu—

Si, Ni, Co, Co—

P, Co—

W—

P, Ni—

P, WN and WSiN;

metal nitrides including TaN, TiN, TaAlN, TiAlN;

metal silicon nitrides;

metal silicides; and

alloys, mixtures or multilayers thereof.

15. The method of claim 1 further including the step of selecting solid dielectric materials of said dielectric matrix from the group consisting of silicon (a-Si:

H), SiO₂, Si₃N₄, SiO_xN_y, SiC, SiCO, SiCOH, and SiCH compounds;

these silicon-containing materials with some or all of the Si replaced by Ge;

carbon-doped oxides;

inorganic oxides, inorganic polymers;

hybrid polymers;

organic polymers;

other carbon-containing materials;

organo-inorganic materials;

diamond-like carbon with or without one or more additives selected from the group consisting of F, N, O, Si, Ge, metals and nonmetals any of the aforementioned materials in porous form, or in a form that changes during processing to or from being porous and/or permeable to being non-porous an/or non-permeable; and

mixtures, multilayers, or layered combinations of the aforementioned materials.

16. The method of claim 1 further including the step of selecting said place-holder material from the group consisting of low thermal stability materials, silicon-containing materials with some or all of the Si replaced by Ge;

carbon-doped oxides;

inorganic oxides, inorganic polymers;

hybrid polymers;

organic polymers;

other carbon-containing materials;

organo-inorganic materials;

diamond-like carbon with or without one or more additives selected from the group containing F, N, O, Si, Ge, metals and nonmetals any of the aforementioned materials in porous form, or in a form that changes during processing to or from being porous and/or permeable to being non-porous and/or non-permeable; and

mixtures, multilayers, or layered combinations of the aforementioned materials.

17. The method of claim 1 further including the step of selecting a bridge layer material from the group consisting of silicon-containing materials the silicon-containing materials with some or all of the Si replaced by Ge;

carbon-doped oxide;

inorganic oxides, inorganic polymers;

hybrid polymers;

organic polymers;

other carbon-containing materials;

organo-inorganic materials;

diamond-like carbon with or without one or more additives selected from the group containing F, N, O, Si, Ge, metals and nonmetals any of the aforementioned materials in porous form, or in a form that changes during processing to or from being porous and/or permeable to being non-porous and/or non-permeable; and

mixtures, multilayers, or layered combinations of the aforementioned materials.

18. The method of claim 1 further including the step of selecting a bridge layer comprised of a lower layer of a dielectric barrier nitride (SiN_x) or silicon carbide (a-Si:

C;

H) and an upper layer of an SiO₂-like material.

19. The method of claim 5 further including the step of selecting a pinch-off dielectric material from the group consisting of silicon-containing materials;

the silicon-containing materials with some or all of the Si replaced by Ge;

carbon-doped oxides;

inorganic oxides, inorganic polymers;

hybrid polymers;

organic polymers, other carbon-containing materials;

organo-inorganic materials, diamond-like carbon with or without one or more additives selected from the group consisting of F, N, O, Si, Ge, metals and nonmetals, any of the aforementioned materials in porous form, or in a form that changes during processing to or from being porous and/or permeable to being non-porous and/or non-permeable;

mixtures, multilayers, or layered combinations of the aforementioned materials.

20. The method of claim 6 wherein said place-holder material is a porous polymer or a nanoporous organo-silicate glass.

21. The method of claim 1 wherein additional conductive material is selectively added to the exposed conductive wiring and vias of a given level after that level'"'"'s dielectric etch-back step.

22. The method of claim 1 wherein extraction of said place-holder material is by supercritical fluid (SCF) extraction.

23. The method of claim 22 wherein said SCF extraction utilizes SCF CO₂, with or without cosolvent additives.

24. The method of claim 1 where the place-holder material is selected to be a thermally decomposable material that can be removed by diffusion through the bridge layer.

25. The method of claim 1 wherein the place-holder material is removed by a process selected from the group consisting of thermal decomposition;

plasma and/or reactive ion etching, with or without heat, in mixtures that may include H, H₂, O, O₂, N, N₂, F, CF₄, other halogen-containing gases or Ar;

wet etching;

vapor HF etching;

laser assisted etching;

microwave-mediated decomposition and removal.