Photogate with improved short wavelength response for a CMOS imager

• US 6,414,342 B1
• Filed: 06/18/1999
• Issued: 07/02/2002
• Est. Priority Date: 06/18/1999
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Rhodes, Howard E.
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US09/335,875
• Time in Patent Office: 1,110 Days
• Field of Search: 257/249, 257/291, 257/292
• US Class Current: 257/291
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/1462 Coatings
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

A photogate-based photosensor for use in a CMOS imager exhibiting improved short wavelength light response. The photogate is formed of a thin conductive layer about 50 to 3000 Angstroms thick. The conductive layer may be a silicon layer, a layer of indium and/or tin oxide, or may be a stack having an indium and/or tin oxide layer over a silicon layer. The thin conductive layer of the photogate permits a greater amount of short wavelength light to pass through the photogate to reach the photosite in the substrate, and thereby increases the quantum efficiency of the photosensor for short wavelengths of light.

Claims

1. A pixel sensor cell for use in an imaging device, said cell comprising:

a doped layer formed in a substrate;

a first doped region formed in said doped layer;

a stacked photogate provided over said first doped region, said stacked photogate comprising a doped polysilicon layer of a thickness within the range of 50 to 800 Angstroms, and a transparent conductive layer on the doped polysilicon layer, wherein the transparent conductive layer is a layer of material selected from the group consisting of indium tin oxide, indium oxide, and tin oxide;

a second doped region for receiving image charge transferred from said first doped region;

a reset transistor for periodically resetting said second doped region to a predetermined potential; and

an output transistor having a gate electrically connected to the second doped region for providing a signal representing image charge transferred to said second doped region.

2. The pixel sensor cell of claim 1, wherein the doped polysilicon layer has a thickness of approximately 300 Angstroms.

3. The pixel sensor cell of claim 1, wherein the transparent conductive layer is a layer of indium tin oxide.

4. The pixel sensor cell of claim 1, wherein the transparent conductive layer is a layer of indium oxide.

5. The pixel sensor cell of claim 1, wherein the transparent conductive layer is a layer of tin oxide.

6. The pixel sensor cell of claim 1, further comprising a transfer gate located between the first and the second doped regions for transferring image charge from said first doped region to said second doped region.

7. The pixel sensor cell of claim 6, wherein the transparent conductive layer extends over a top surface of the transfer gate.

8. The pixel sensor cell of claim 1, wherein the doped layer is doped to a first conductivity type.

9. The pixel sensor cell of claim 8, wherein the first conductivity type is p-type.

10. The pixel sensor cell of claim 1, wherein the first and the second doped regions are doped to a second conductivity type.

11. The pixel sensor cell of claim 10, wherein the second conductivity type is n-type.

12. An array of pixel sensor cells comprising:

a doped layer formed in a substrate;

a plurality of pixel sensor cells formed in said doped layer, wherein each pixel sensor cell has a photogate comprising a silicon layer of a thickness within the range of 50 to 800 Angstroms and a transparent conductive layer on the silicon layer, wherein the transparent conductive layer is a layer of material selected from the group consisting of indium tin oxide, indium oxide, and tin oxide.

13. The array of claim 12, wherein the silicon layer is a layer of doped polysilicon.

14. The array of claim 12, wherein the silicon layer has a thickness of approximately 300 Angstroms.

15. The array of claim 12, wherein the transparent conductive layer is a layer of indium tin oxide.

16. The array of claim 12, wherein the transparent conductive layer is a layer of indium oxide.

17. The array of claim 12, wherein the transparent conductive layer is a layer of tin oxide.

18. An imaging system for generating output signals based on an image focused on the imaging system, comprising:

a plurality of pixel cells arranged into an array of rows and columns, each pixel cell being operable to generate a voltage at a diffusion node corresponding to detected light intensity by the cell, wherein each pixel cell has a photogate comprising a transparent conductive layer of doped polysilicon having a thickness within the range of 50 to 3000 Angstroms, and a transparent oxide layer on the transparent conductive layer, wherein the transparent oxide layer is a layer of material selected from the group consisting of indium tin oxide, indium oxide, and tin oxide;

a row decoder having a plurality of control lines connected to the cell array, each control line being connected to the cells in a respective row, wherein the row decoder is operable to activate the cells in a row; and

a plurality of output circuits each including a respective output transistor, each output circuit being connected to a respective cell of said array, each circuit being operable to store voltage signals received from a respective cell and to provide a cell output signal.

19. The imaging system of claim 18, wherein the doped polysilicon layer has a thickness within the range of 50 to 800 Angstroms.

20. The imaging system of claim 18, wherein the transparent oxide layer has a thickness within the range of 100 to 3000 Angstroms.