Mini FLASH process and circuit

• US 6,414,351 B2
• Filed: 01/09/2001
• Issued: 07/02/2002
• Est. Priority Date: 09/03/1998
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Green, James E., Clampitt, Darwin A.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US09/757,520
• Publication Number:
  US 20010002055A1
• Time in Patent Office: 539 Days
• Field of Search: 438/211, 438/258, 438/257, 438/264, 438/266, 257/315, 257/321
• US Class Current: 257/315
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for making reduced-size FLASH EEPROM memory circuits, and to the resulting memory circuit. An FET integrated circuit having two different gate oxide thicknesses deposited at a single step, where a portion of the thickness of the thicker oxide is formed, that oxide is removed from the area of the chip to have the thinner oxide, then the rest of the thicker oxide is grown during the time that the thinner oxide is grown on the area of the chip to have the thinner oxide. Layers for the floating gate stacks are deposited. Trenches are etched in a first, and then a second perpendicular direction, and the perpendicular sides of the stacks are covered with vertical-plane nitride layers in two separate operations. Tungsten word lines and bit contacts are deposited. Aluminum-copper lines are deposited on the bit lines.

Claims

1. An information handling system comprising:

a processor;

an input/output subsystem coupled to the processor; and

a data storage memory coupled to the processor, the memory including an electronic data storage circuit, the circuit including;

a first set of one or more transistors each having a gate dielectric of a first thickness;

a second set of one or more transistors each having a gate dielectric layer of a second thickness thinner than the first thickness;

a floating-gate poly layer over the dielectric layer of the second set of one or more transistors;

an inter-poly nitride layer over the floating-gate poly layer;

a control-gate poly layer over the inter-poly nitride layer;

a tungsten-silicide (WSix) layer over the control-gate poly layer, wherein the gate dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer form a floating-gate stack on a silicon substrate, the stack having a first side facing a first trench that extends into the silicon substrate and a second side facing a second trench that extends into the silicon substrate, and a drain end and a source end;

a nitride layer covering the first side of the stack from the inter-poly nitride layer to the first trench;

a nitride layer covering the second side of the stack from the inter-poly nitride layer to the second trench;

a nitride layer covering the drain end from the inter-poly nitride layer to the substrate; and

a nitride layer covering the source end from the inter-poly nitride layer to the substrate.

2. The system according claim 1, further comprising:

a display unit coupled to the processor.

3. The system according claim 2, wherein the circuit further includes:

a tungsten drain contact formed substantially adjacent to the nitride layer covering the drain end;

a tungsten source contact formed substantially adjacent to the nitride layer covering the source end; and

a tungsten gate contact formed to substantially contact the WSix layer.

4. The system according claim 1, wherein the circuit further includes:

a tungsten drain contact formed substantially adjacent to the nitride layer covering the drain end;

a tungsten source contact formed substantially adjacent to the nitride layer covering the source end; and

a tungsten gate contact formed to substantially contact the WSix layer.

5. The system according to claim 4, wherein the circuit further includes:

an aluminum-copper (AlCu) line formed substantially in contact with the tungsten drain contact.

6. An information handling system comprising:

a processor;

an input/output subsystem coupled to the processor; and

a data storage memory coupled to the processor, the memory including an electronic data storage circuit, the circuit including;

a first set of one or more transistors each having a gate dielectric of a first thickness;

a second set of one or more transistors each having a gate dielectric layer of a second thickness thinner than the first thickness;

a third set of one or more transistors each having a gate dielectric layer of a third thickness thicker than the first thickness;

a floating-gate poly layer over the gate dielectric layer of the second set of one or more transistors;

an inter-poly nitride layer over the floating-gate poly layer;

a control-gate poly layer over the inter-poly nitride layer;

a tungsten-silicide (WSix) layer over the control-gate poly layer, wherein the gate dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer form a floating-gate stack on a silicon substrate, the stack having a first side facing a first trench that extends into the silicon substrate and a second side facing a second trench that extends into the silicon substrate, and a drain end and a source end;

a nitride layer covering the first side of the stack from the inter-poly nitride layer to the first trench;

a nitride layer covering the second side of the stack from the inter-poly nitride layer to the second trench;

a nitride layer covering the drain end from the inter-poly nitride layer to the substrate; and

a nitride layer covering the source end from the inter-poly nitride layer to the substrate.

7. The system according claim 6, further comprising:

a display unit coupled to the processor.

8. An information handling system comprising:

a processor;

an input/output subsystem coupled to the processor; and

a data storage memory coupled to the processor, the memory including an electronic data storage circuit, the circuit including;

a first set of one or more transistors each having a gate dielectric of a first thickness;

a second set of one or more transistors each having a gate dielectric layer of a second thickness thinner than the first thickness;

a third set of one or more transistors each having a gate dielectric layer of a third thickness thicker than the first thickness;

a floating-gate poly layer over the gate dielectric layer of the second set of one or more transistors;

an inter-poly nitride layer over the floating-gate poly layer;

a control-gate poly layer over the inter-poly nitride layer;

a tungsten-silicide (WSix) layer over the control-gate poly layer, wherein the gate dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer form a floating-gate stack on a silicon substrate, the stack having a first side facing a first trench that extends into the silicon substrate and a second side facing a second trench that extends into the silicon substrate, and a drain end and a source end;

a nitride layer covering the first side of the stack from the inter-poly nitride layer to the first trench;

a nitride layer covering the second side of the stack from the inter-poly nitride layer to the second trench;

a nitride layer covering the drain end from the inter-poly nitride layer to the substrate;

a nitride layer covering the source end from the inter-poly nitride layer to the substrate;

a tungsten drain contact formed substantially adjacent to the nitride layer covering the drain end;

a tungsten source contact formed substantially adjacent to the nitride layer covering the source end; and

a tungsten gate contact formed to substantially contact the WSix layer.

9. The system according claim 8, further comprising:

a display unit coupled to the processor.

10. An information handling system comprising:

a processor;

an input/output subsystem coupled to the processor; and

a data storage memory coupled to the processor, the memory including an electronic data storage circuit, the circuit including;

a first set of one or more transistors each having a gate dielectric of a first thickness;

a second set of one or more transistors each having a gate dielectric layer of a second thickness thinner than the first thickness;

a third set of one or more transistors each having a gate dielectric layer of a third thickness thicker than the first thickness;

a floating-gate poly layer over the gate dielectric layer of the second set of one or more transistors;

an inter-poly nitride layer over the floating-gate poly layer;

a control-gate poly layer over the inter-poly nitride layer;

a tungsten-silicide (WSix) layer over the control-gate poly layer, wherein the gate dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer form a floating-gate stack on a silicon substrate, the stack having a first side facing a first trench that extends into the silicon substrate and a second side facing a second trench that extends into the silicon substrate, and a drain end and a source end;

a nitride layer covering the first side of the stack from the inter-poly nitride layer to the first trench;

a nitride layer covering the second side of the stack from the inter-poly nitride layer to the second trench;

a nitride layer covering the drain end from the inter-poly nitride layer to the substrate;

a nitride layer covering the source end from the inter-poly nitride layer to the substrate;

a tungsten drain contact formed substantially adjacent to the nitride layer covering the drain end;

a tungsten source contact formed substantially adjacent to the nitride layer covering the source end;

a tungsten gate contact formed to substantially contact the WSix layer; and

an aluminum-copper (AlCu) line formed substantially in contact with the tungsten drain contact.

11. The system according claim 10, further comprising:

a display unit coupled to the processor.

12. An information handling system comprising:

a processor;

an input/output subsystem coupled to the processor; and

a data storage memory coupled to the processor, the memory including an electronic data storage circuit, the circuit including;

a first set of one or more transistors each having a gate dielectric layer of a first thickness;

a floating-gate poly layer over the dielectric layer;

an inter-poly nitride layer over the floating-gate poly layer;

a control-gate poly layer over the inter-poly nitride layer;

a tungsten-silicide (WSix) layer over the control-gate poly layer, wherein the gate dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer form a floating-gate stack on a silicon substrate, the stack having a first side facing a first trench that extends into the silicon substrate and a second side facing a second trench that extends into the silicon substrate, and a drain end and a source end;

a nitride layer covering the first side of the stack from the inter-poly nitride layer to the first trench;

a nitride layer covering the second side of the stack from the inter-poly nitride layer to the second trench;

a nitride layer covering the drain end from the inter-poly nitride layer to the substrate;

a nitride layer covering the source end from the inter-poly nitride layer to the substrate;

a tungsten drain contact formed substantially adjacent to the nitride layer covering the drain end;

a tungsten source contact formed substantially adjacent to the nitride layer covering the source end;

a tungsten gate contact formed to substantially contact the WSix layer;

a barrier layer between the tungsten drain contact and the substrate to prevent migration of the tungsten; and

a barrier layer between the tungsten source contact and the substrate to prevent migration of the tungsten.

13. The system according claim 12, further comprising:

a display unit coupled to the processor.

14. The system according claim 12, further comprising:

a second set of one or more transistors each having a gate dielectric layer of a second thickness thicker than the first thickness.

15. The system according claim 14, further comprising:

a third set of one or more transistors each having a gate dielectric layer of a third thickness thicker than the second thickness.

16. An information handling system comprising:

a processor;

an input/output subsystem coupled to the processor; and

a data storage memory coupled to the processor, the memory including an electronic data storage circuit, the circuit including;

a set of one or more transistors each having a gate dielectric layer;

a floating-gate poly layer over the dielectric layer;

an inter-poly nitride layer over the floating-gate poly layer;

a control-gate poly layer over the inter-poly nitride layer;

a tungsten-silicide (WSix) layer over the control-gate poly layer, wherein the gate dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer form a floating-gate stack on a silicon substrate, the stack having a first side facing a first trench that extends into the silicon substrate and a second side facing a second trench that extends into the silicon substrate, and a drain end and a source end;

a nitride layer covering the first side of the stack from the inter-poly nitride layer to the first trench;

a nitride layer covering the second side of the stack from the inter-poly nitride layer to the second trench;

a nitride layer covering the drain end from the inter-poly nitride layer to the substrate;

a nitride layer covering the source end from the inter-poly nitride layer to the substrate;

a tungsten drain contact formed substantially adjacent to the nitride layer covering the drain end;

a tungsten source contact formed substantially adjacent to the nitride layer covering the source end;

a tungsten gate contact formed to substantially contact the WSix layer, wherein the tungsten gate contact and the tungsten source contact are planarized to a common upper plane.

17. The system according claim 16, further comprising:

a display unit coupled to the processor.

18. The system according claim 16, further comprising:

a second set of one or more transistors each having a gate dielectric layer of a second thickness thicker than the first thickness.

19. The system according claim 18, further comprising:

a third set of one or more transistors each having a gate dielectric layer of a third thickness thicker than the second thickness.

20. An information handling system comprising:

a processor;

an input/output subsystem coupled to the processor; and

a data storage memory coupled to the processor, the memory including an electronic data storage circuit, the circuit including;

a set of one or more transistors each having a gate dielectric layer;

a floating-gate poly layer over the dielectric layer;

an inter-poly nitride layer over the floating-gate poly layer;

a control-gate poly layer over the inter-poly nitride layer;

a tungsten-silicide (WSix) layer over the control-gate poly layer, wherein the gate dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer form a floating-gate stack on a silicon substrate, the stack having a first side facing a first trench that extends into the silicon substrate and a second side facing a second trench that extends into the silicon substrate, and a drain end and a source end;

a nitride layer covering the first side of the stack from the inter-poly nitride layer to the first trench;

a nitride layer covering the second side of the stack from the inter-poly nitride layer to the second trench;

a nitride layer covering the drain end from the inter-poly nitride layer to the substrate;

a nitride layer covering the source end from the inter-poly nitride layer to the substrate;

a tungsten drain contact formed substantially adjacent to the nitride layer covering the drain end;

a tungsten source contact formed substantially adjacent to the nitride layer covering the source end;

a tungsten gate contact formed to substantially contact the WSix layer, wherein the tungsten gate contact and the tungsten source contact are deposited simultaneously and then are planarized to a common upper plane.

21. The system according claim 20, further comprising:

a display unit coupled to the processor.

22. The system according claim 20, further comprising:

a second set of one or more transistors each having a gate dielectric layer of a second thickness thicker than the first thickness.

23. The system according claim 22, further comprising:

a third set of one or more transistors each having a gate dielectric layer of a third thickness thicker than the second thickness.