Semiconductor device including edge bond pads and methods

• US 6,414,374 B2
• Filed: 05/22/2001
• Issued: 07/02/2002
• Est. Priority Date: 12/31/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kinsman, Larry D., Farnworth, Warren M., Moden, Walter L.
• Primary Examiner(s): Tran, Minh Loan
• Assistant Examiner(s): THAI, LUAN C
• Application Number:
  US09/862,942
• Publication Number:
  US 20010022393A1
• Time in Patent Office: 406 Days
• Field of Search: 257/723, 257/780, 257/618, 257/620, 257/622, 257/623, 257/626, 257/690, 257/735, 257/786
• US Class Current: 257/620
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/03602 Mechanical treatment, e.g. polishing, grinding
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32227 the layer connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/8114 Guiding structures outside the body
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8314 Guiding structures outside the body
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/72 : Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A vertically mountable semiconductor device including at least one bond pad disposed on an edge thereof. The bond pad includes a conductive bump disposed thereon. The semiconductor device may also include a protective overcoat layer. The present invention also includes a method of fabricating the semiconductor device, including forming disconnected notches in a semiconductor wafer, redirecting circuit traces into each of the notches, and singulating the semiconductor wafer along the notches to form bond pads on the edges of the resultant semiconductor devices. A method of attaching the semiconductor device to a carrier substrate includes orienting the semiconductor device such that the bond pad is aligned with a corresponding terminal of the carrier substrate, and establishing an electrical connection between the bond pad and the terminal. Preferably, an electrically conductive material is disposed between the bond pad and the terminal to establish an electrically conductive bond between the semiconductor device and the carrier substrate.

Claims

1. A semiconductor die, comprising:

an active surface;

a first layer comprising protective material over said active surface;

a plurality of peripheral edges, at least one peripheral edge of said plurality of peripheral edges including at least one disconnected notch formed in at least a portion thereof, said at least one disconnected notch extending from a portion of said active surface of the semiconductor die and terminating at said at least one peripheral edge;

at least one circuit trace traversing a portion of said first layer to said at least one disconnected notch;

at least one bond pad disposed at least partially on said at least one circuit trace and forming a connector for mounting the semiconductor die nonparallel relative to a substrate with said at least one bond pad contacting a portion of said substrate; and

a second layer comprising protective material covering at least a portion of said first layer and at least a portion of said at least one circuit trace.

2. The semiconductor die of claim 1, wherein said at least one bond pad comprises solder.

3. The semiconductor die of claim 1, comprising a plurality of bond pads.

4. The semiconductor die of claim 3, wherein each of said plurality of bond pads is disposed on a single peripheral edge of said plurality of peripheral edges.

5. A chip-on-board assembly, comprising:

a carrier substrate having at least one conductive terminal thereon; and

a semiconductor die mountable on said carrier substrate, said semiconductor die including;

an active surface;

a first layer of protective material covering at least a portion of said active surface;

a plurality of edges forming a periphery of said semiconductor die, at least one edge of said plurality of edges including a disconnected notch formed in at least a portion thereof, said disconnected notch extending from a portion of the active surface of said semiconductor die and terminating at said at least one edge;

at least one circuit trace extending onto at least a portion of said disconnected notch;

a second layer of protective material covering said at least a portion of said active surface and at least a portion of said at least one circuit trace; and

at least one bond pad disposed at least partially on said at least one circuit trace, said at least one bond pad forming a connector for mounting said semiconductor die nonparallel relative to said carrier substrate, said at least one bond pad located correspondingly to said at least one conductive terminal.

6. The chip-on-board assembly of claim 5, further comprising a quantity of electrically conductive material disposed between said at least one bond pad and said at least one conductive terminal.

7. The chip-on-board assembly of claim 6, wherein said quantity of electrically conductive material comprises a z-axis elastomer.

8. The chip-on-board assembly of claim 6, wherein said quantity of electrically conductive material comprises solder.

9. The chip-on-board assembly of claim 5, wherein said at least one bond pad and said at least one conductive terminal communicate by way of an interference contact.

10. The chip-on-board assembly of claim 5, further comprising an alignment device disposed on said carrier substrate, said semiconductor die being at least partially disposable within a receptacle of said alignment device.

11. The chip-on-board assembly of claim 10, wherein said alignment device aligns said at least one bond pad with said at least one conductive terminal upon disposal of said semiconductor die at least partially within said receptacle.

12. The chip-on-board assembly of claim 5, wherein, upon assembly of said semiconductor die with said carrier substrate, at least a portion of said at least one bond pad contacts at least a portion of said at least one conductive terminal.

13. The chip-on-board assembly of claim 5, wherein said semiconductor die comprises an overcoat layer over at least a portion of at least said active surface thereof.

14. A semiconductor die, comprising:

an active surface;

a first protective layer covering at least a portion of said active surface;

a plurality of edges forming a periphery of said semiconductor die, a single edge of said plurality of edges including a disconnected notch formed therein, said disconnected notch extending from a portion of said active surface of the semiconductor die and terminating at said single edge;

at least one circuit trace extending onto at least a portion of said disconnected notch;

a second protective layer covering at least a portion of said active surface and at least a portion of said at least one circuit trace; and

a bond pad disposed at least partially on said at least one circuit trace, said bond pad forming a connector for mounting said semiconductor die nonparallel relative to a carrier substrate.

15. The semiconductor die of claim 14, wherein, upon assembly of said semiconductor die with said carrier substrate, at least a portion of said bond pad contacts at least a portion of at least one conductive terminal of said carrier substrate.

16. The semiconductor die of claim 14, further comprising an overcoat layer over over at least a portion of at least said active surface.

17. The semiconductor die of claim 14, wherein said bond pad comprises solder.

18. The semiconductor die of claim 14, comprising a plurality of notches and a corresponding plurality of bond pads therein.