Level shifter for ultra-deep submicron CMOS designs

• US 6,414,534 B1
• Filed: 02/20/2001
• Issued: 07/02/2002
• Est. Priority Date: 02/20/2001
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chung-Hui, Wang, Wen-Tai
• Primary Examiner(s): Cunningham, Terry D.
• Assistant Examiner(s): NGUYEN, LONG T
• Application Number:
  US09/784,819
• Time in Patent Office: 497 Days
• Field of Search: 327/333, 327/52, 327/55, 327/57, 327/427, 327/434, 327/437, 326/63, 326/68, 326/80, 326/81
• US Class Current: 327/333
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03K 3/356182 with additional means for controlling the main nodes

Abstract

New level shifting circuits, one using dynamic current compensation and one using dynamic voltage equalization, are described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter input is connected to the input of the level shifting circuit to form an inverted level shifting input. A first NMOS transistor has the gate tied to the level shifting input and the source tied to ground. A first PMOS transistor has the gate tied to the level shifting output, the source tied to the high supply, and the drain tied to the first NMOS drain. A second NMOS transistor has the gate tied to the inverted level shifter input, the source tied to the ground, and the drain tied to the level shifting output. A second PMOS transistor has the gate tied to the first NMOS drain, the source tied to the high supply, and the drain is tied to the level shifting output. A third NMOS transistor has the gate tied to the first NMOS drain, v source tied to the level shifting input, and the drain tied to the level shifting output. A fourth NMOS transistor has the gate tied to the second NMOS drain, the source tied to the inverted level shifting input, and the drain tied to the first NMOS drain.

Claims

1. A level shifting circuit comprising:

a circuit input that swings between a low supply and ground;

a circuit output that swings between a high supply and said ground;

an inverter with input connected to said circuit input and output forming inverted circuit input;

a first NMOS transistor with gate connected to said circuit input and with source connected to said ground;

a first PMOS transistor with gate connected to said circuit output, with source connected to said high supply, and with drain connected to said first NMOS transistor drain;

a second NMOS transistor with gate connected to said inverted circuit input, with source connected to said ground, and with drain connected to said circuit output;

a second PMOS transistor with gate connected to said first NMOS transistor drain, with source connected to said high supply, and with drain connected to said circuit output;

a third NMOS transistor with gate connected to said first NMOS transistor drain, with source connected to said circuit input, and with drain connected to said circuit output; and

a fourth NMOS transistor with gate connected to said second NMOS transistor drain, with source connected to said inverted circuit input, and with drain connected to said first NMOS transistor drain.

2. The circuit according to claim 1 wherein said inverter comprises an NMOS transistor and a PMOS transistor.

3. The circuit according to claim 2 wherein said NMOS transistor and said PMOS transistor are low voltage transistors.

4. The circuit according to claim 1 wherein said first NMOS transistor, said second NMOS transistor, said first PMOS transistor, and said second PMOS transistor are high voltage transistors.

5. The circuit according to claim 1 wherein said third NMOS transistor and said fourth NMOS transistor are high voltage transistors.

6. The circuit according to claim 1 wherein said low supply is between about 0.5 Volts and 2.5 Volts.

7. The circuit according to claim 1 wherein said high supply is between about 1 Volt and 30 Volts.