Gate driving circuit in liquid crystal display

• US 6,414,670 B1
• Filed: 03/31/1999
• Issued: 07/02/2002
• Est. Priority Date: 08/24/1998
• Status: Expired due to Term

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: LG Semicon Co Ltd (SK Hynix Inc.)
• Inventors: Kim, Byung Doo
• Primary Examiner(s): Wu, Xiao
• Assistant Examiner(s): ZAMANI, ALI A
• Application Number:
  US09/282,159
• Time in Patent Office: 1,189 Days
• Field of Search: 345/98, 345/99, 345/100, 345/211, 345/213, 345/87
• US Class Current: 345/98
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

A gate driving circuit in a liquid crystal display is disclosed which can minimize a power consumption by avoiding unnecessary drive of gate line drivers. The gate driving circuit is used in a liquid crystal display having a liquid crystal panel with thin film transistors and pixel electrodes for displaying an image, a source driving circuit for applying video data to a source line in the liquid crystal panel, and a gate driving circuit for applying a driving signal to a gate line in the thin film transistors. The gate driving circuit includes a plurality of gate line drivers connected in series for applying the driving signal to the gate line, and a plurality of clock generation controlling units corresponding to the plurality of gate line drivers each for controlling a timing of a clock signal to a respective gate line driver, thereby controlling a driving timing of the respective gate line driver.

Claims

1. A gate driving circuit in a liquid crystal display having a liquid crystal panel with thin film transistors and pixel electrodes for displaying an image, a source driving circuit for applying video data to a source line in the liquid crystal panel, and a gate driving circuit for applying a driving signal to a gate line in the thin film transistors, the gate driving circuit comprising:

a plurality of gate line drivers connected in series for applying the driving signal to the gate line; and

a plurality of clock generation controlling units corresponding to the plurality of gate line drivers each for controlling a timing of a clock signal to a respective gate line driver and each including a first flip flop connected as a toggle flip flop, thereby controlling a driving timing of the respective gate line driver.

2. The gate driving circuit as claimed in claim 1, wherein each of the plurality of clock generation controlling units is provided either within the respective gate line driver or outside of the respective gate line driver.

3. The gate driving circuit as claimed in claim 1, wherein each of the plurality of clock generation controlling unit includes:

the first flipflop being operative triggered at a rising edge of the clock signal;

a second flipflop being operative triggered at a falling edge of the clock signal;

an inverter for inverting an output of the second flipflop;

a first logic device for subjecting an output of the inverter and an output of the first flipflop to a logical operation; and

a second logic device for subjecting an output of the first logic device and an external clock signal to a logical operation.

4. The gate driving circuit as claimed in claim 3, wherein the first and second logic devices are AND gates.

13. The gate driving circuit as claimed in claim 1, further including a second flip flop connected as a toggle flip flop.

5. A gate driving circuit in a liquid crystal display having a liquid crystal panel for displaying an image, a gate driving circuit for applying a driving signal in a row direction of the liquid crystal panel, and a source driving circuit for applying a data signal in a column direction of the liquid crystal panel, the gate driving circuit comprising:

a plurality of gate line drivers connected in series for applying the driving signal to gate lines; and

,

a plurality of clock generation controlling units each for controlling a provision timing of a clock signal to a respective gate line driver in response to a first control signal and each including a first flip flop connected as a toggle flip flop, thus driving the plurality of gate line drivers in succession, and in response to a second control signal for shifting the plurality of gate line drivers in succession.

6. The gate driving circuit as claimed in claim 5, wherein the first control signal is a signal for enabling the respective gate line driver, and the second control signal is a signal from the respective gate line driver to which the first control signal is provided, for enabling a next gate line driver.

7. The gate driving circuit as claimed in claim 6, wherein the respective gate line driver to which the first control signal is provided provides driving signals to the gate lines in succession synchronized to the clock signal from the clock generation controlling unit, and provides the second control signal once a last driving signal is provided.

8. The gate driving circuit as claimed in claim 5, wherein each of the plurality of clock generation controlling units includes:

the first flipflop being operative triggered at a rising edge of the clock signal;

a second flipflop being operative triggered at a falling edge of the clock signal;

an inverter for inverting an output of the second flipflop;

a first logic device for subjecting an output of the inverter and an output of the first flipflop to a logical operation; and

a second logic device for subjecting an output of the first logic device and an external clock signal to a logical operation.

9. The gate driving circuit as claimed in claim 8, wherein the first and second logic devices are AND gates.

10. The gate driving circuit as claimed in claim 5, wherein each of the plurality of clock generation controlling units is provided either within the respective gate line driver or outside of the respective gate line driver.

14. The gate driving circuit as claimed in claim 5, wherein each clock generation controlling unit includes a second flip flop connected as a toggle flip flop.

11. A gate driving circuit in a liquid crystal display having a liquid crystal panel for displaying an image, a gate driving circuit for applying a driving signal in a row direction of the liquid crystal panel, and a source driving circuit for applying a data signal in a column direction of the liquid crystal panel, the gate driving circuit comprising:

a plurality of gate line drivers connected in series for applying the driving signal to gate lines in the liquid crystal panel;

a first flipflop being operative in response to a first control signal which enables a respective gate line driver as a clock signal;

a second flipflop being operative in response to a second control signal from the respective gate line driver as a clock signal for enabling a next gate line driver after finishing enabling the respective gate line driver;

an inverter connected to an output terminal on the second flipflop;

a first logic device for subjecting an output of the inverter and an output of the first flipflop to a logical operation, and generating a reset signal for the first and second filpflops; and

a second logic device for subjecting an output of the first logic device and an external clock signal to a logical operation, and for selectively providing an output signal to the respective gate line driver.

12. The gate driving circuit as claimed in claim 11, wherein the respective gate line driver is triggered at a rising edge of the output signal from the second logic device to provide a driving signal to the gate lines in succession, and provides the second control signal to be used as a clock signal for the second flipflop once a last driving signal is provided.

15. The gate driving circuit as claimed in claim 11, wherein the first flip flop is connected as a toggle flip flop.

16. The gate driving circuit as claimed in claim 11, wherein the second flip flop is connected as a toggle flip flop.