Register setting-micro programming system

• US 6,414,687 B1
• Filed: 02/18/1998
• Issued: 07/02/2002
• Est. Priority Date: 04/30/1997
• Status: Expired due to Term

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Gibson, Ian
• Primary Examiner(s): Chauhan, Ulka J.
• Application Number:
  US09/025,507
• Time in Patent Office: 1,595 Days
• Field of Search: 345/501-506, 345/520, 345/521, 345/513, 345/514, 345/202, 345/559, 710/8, 710/14, 712/32, 712/33, 712/42, 712/43, 712/208, 712/229
• US Class Current: 345/503
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/00 3D [Three Dimensional] image rendering

Abstract

A graphics processor includes a plurality of interrelated functional modules and at least one register associated with each of the functional modules. The plurality of interrelated functional modules are interconnected by a data pipeline for conveying data, and each register is configured to control a function of its associated functional module. The graphics processor also includes a control bus interconnecting each of the registers for conveying instructions, and an instruction controller for decoding instructions for use with the graphics processor. The control bus and the data pipeline are physically separate, and the instruction controller includes a register setting unit adapted to set the registers via the control bus in accordance with a decoded instruction. This enables the function of each of the functional modules to be configured in response to each instruction.

Claims

1. A graphics processor comprising:

a plurality of interrelated functional modules, wherein the plurality of interrelated functional modules are interconnected by a data pipeline for conveying data;

at least one register associated with each of the functional modules, each register being configured to control a function of its associated functional module;

a control bus interconnecting each of the registers for conveying instructions, wherein said control bus and the data pipeline are physically separate; and

an instruction controller for decoding instructions for use with the graphics processor, the instruction controller including a register setting unit adapted to set the registers via the control bus in accordance with a decoded instruction, thereby to configure the function of each of the functional modules in response to each instruction.

2. A graphics processor according to claim 1, wherein at least some of the registers include a semaphore access mechanism accessible by external modules, including the functional modules.

3. A graphics processor according to claim 1 or claim 2, wherein at least some of the registers include a status register and an associated register, the contents of each status register being updateable by its associated register during or following execution of an instruction.

4. A graphics processor according to claim 1, wherein each one of the functional modules provides a signal indicative of whether it is actively processing data.

5. A graphics processor according to claim 1, wherein the register setting unit is one of a plurality of units able to set register values, and the graphics processor further includes an arbitrator unit adapted to control which of the units are able to set register values at a given time.

6. A graphics processor according to claim 1, wherein the values of the registers are set in a predetermined order.

7. A graphics processor according to claim 6, wherein the predetermined order varies according to a particular instruction being implemented.

8. A graphics processor according to claim 1, wherein each functional module includes error, interrupt, and exception signal outputs, which are asserted when an error, interrupt, or exception, respectively, occurs in relation to a module in question.

9. A graphics processor according to claim 1, further including:

a control bus access unit associated with each of the functional modules, wherein the control bus access units enable the functional modules selectively to interact with the control bus.

10. A graphics processor according to claim 1, including a multi-used RAM for storing:

(a) interval and fractional tables of data points, during colour conversion operations;

(b) matrix coefficient data during image transformations and convolutions; and

(c) double buffered minimal code units during JPEG operations.

11. A graphics processor according to claim 10, wherein said interval and fractional tables are stored on demand in the multi-used RAM.

12. A graphics processor according to claim 1, further including:

a JPEG unit adapted to perform JPEG encoding and decoding; and

a cache normally utilised for storing recently-used data and being adapted to store JPEG tables when the graphics processor is performing JPEG operations.

13. A graphics processor according to claim 12, wherein the cache is also utilised for storing Huffman tables for access by the graphics processor when performing JPEG operations.

14. A graphics processor according to claim 12 or claim 13, wherein the JPEG unit may independently be utilised for general Huffman encoding and decoding, and the cache may be utilised for storing tables for Huffman encoding and decoding.

15. A graphics processor according to claim 14, wherein the JPEG unit is utilised for Photo-CD decoding of images.

16. A graphics processor according to claim 12, wherein the JPEG unit is able to decode a stream of Huffman symbols at a rate of one symbol per clock cycle.

17. A graphics processor according to claim 12, further including a coprocessor that includes a coefficients coder attached to a buffer, the coefficients coder being configured selectively to write data to the buffer in zigzag order and to read data from the buffer in sequential order, and vice versa.

18. A graphics processor according to claim 12, wherein the JPEG unit decodes a stream of JPEG data and includes a facility for discarding an initial portion of a decoded JPEG stream and limiting a volume of output from the JPEG stream.

19. A graphics processor according to claim 12, wherein the JPEG unit is configured to pad a stream of data to be JPEG encoded.

20. A graphics processor according to claim 19, wherein the JPEG unit pads the stream of data to be JPEG encoded by automatically padding irregularly sized MCUs to be at least 8×

8 in size.

21. A method of processing graphics in a graphics processor, comprising the steps of:

providing a plurality of interrelated functional modules, wherein the plurality of interrelated functional modules are interconnected by a data pipeline for conveying data;

providing at least one register associated with each of the functional modules, each register being configured to control a function of its associated functional module;

providing a control bus interconnecting each of the registers for conveying instructions, wherein the control bus and the data pipeline are physically separate;

decoding an instruction for use with the graphics processor; and

setting the registers via the control bus in accordance with the decoded instruction, thereby to configure the function of each of the functional modules in response to each instruction.

22. A system comprising:

an input device;

a graphics processor adapted to receive graphics input data from said input device, the graphics processor comprising;

a plurality of interrelated functional modules, wherein the plurality of interrelated functional modules are interconnected by a data pipeline for conveying data,

at least one register associated with each of the functional modules, each register being configured to control a function of its associated functional module,

a control bus interconnecting each of the registers for conveying instructions, wherein said control bus and the data pipeline are physically separate, and

an instruction controller for decoding instructions for use with the graphics processor, the instruction controller including a register setting unit adapted to set the registers via the control bus in accordance with a decoded instruction, thereby to configure the function of each of the functional modules in response to each instruction; and

an output device adapted to receive graphics output data from the graphic processor.