Device for identifying packets of digital data and a receiver for digital television signals equipped with such a device

• US 6,414,726 B1
• Filed: 10/31/1997
• Issued: 07/02/2002
• Est. Priority Date: 11/01/1996
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chauvel, Gerard
• Primary Examiner(s): Miller, John W.
• Assistant Examiner(s): Lo, Linus H.
• Application Number:
  US08/961,958
• Time in Patent Office: 1,705 Days
• Field of Search: H04/N.5458, 348/726, 348/465, 348/461, 348/725, 348/425.1, 348/714, 348/399.1, 370/423, 370/464, 370/465
• US Class Current: 348/726
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42615 involving specific demultiplexing arrangements
• CPC Class Codes: H04N 21/42623 involving specific decryption arrangements
• CPC Class Codes: H04N 21/42653 for processing graphics
• CPC Class Codes: H04N 21/431 Generation of visual interfaces for content selection or interaction; Content or additional data rendering
• CPC Class Codes: H04N 21/434 Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/439 Processing of audio elementary streams
• CPC Class Codes: H04N 21/44 Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
• CPC Class Codes: H04N 21/443 OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB

Abstract

Circuitry for identifying digital data packets, each comprising a useful signal and a header signal containing data pertaining to the contents of the useful signal is provided. The circuitry includes a means (30) for extracting data from each header signal, which data is representative of a corresponding useful signal, a means for storing reference data in a memory, at addresses each corresponding to a packet type, and a means for comparing the data extracted from each header signal with said reference data stored in memory, and for the delivery, to a data processing unit (32,34), of an address signal indicating the nature of the corresponding packet. The data storage means and the comparison means preferably employ an associative memory (38) adapted to ensure the simultaneous comparison of the data extracted from each header signal with the reference data stored in memory.

Claims

1. Packet identification circuitry, comprising:

packet header decoder for extracting a portion of data from a packet header, said portion indicating at least a certain packet type; and

associative memory coupled to said decoder for storing reference data corresponding to a plurality of packet types, for simultaneously determining if a piece of said portion of data matches any one of said reference data stored in said memory, and for outputting a signal representative of said matching, wherein the associative memory comprises an input port coupled to the packet header decoder to receive the portion of data extracted from a packet header and a network of rows and columns of memory cells each comprising;

a set of charge transistors for storing the reference data received on the input port, such that each row stores a byte of reference data corresponding to one of the plurality of packet types; and

a set of transistors assembled as a comparator ensuing the simultaneous comparison between the portion of data extracted from a packet header and of the reference data stored in the charge transistors so as to deliver, when a reference byte stored in a memory cell row is identical to a byte present on the input port, a pairing signal to an address coding system for indicating which row contained the identical reference byte.

2. An electronic device for identifying packets (10) of digital data, with each packet continuing a useful signal (14) and a header signal (12) containing data about the contents of the useful signal (14), comprising:

a means (30) for extracting a portion of data from each header signal, which is representative of the nature of the corresponding usefull signal (14);

memory storage means (38,44,46) for reference data, at addresses each corresponding to one packet type; and

comparison means (T3,T4,T5) for comparing the piece of data extracted from each header signal (12) with said reference data stored in memory and delivering data to a data processing unit (32,34) of an address signal indicating the type of the corresponding packet (10), wherein the memory storage means and the comparison means consist of an associative memory (38) adapted to ensure the simultaneous comparison of the piece of data extracted from each header signal with the reference data stored in memory, wherein the associative memory (38) comprises a network of rows and columns of memory cells each comprising a set of charge transistors (44,46) for the storage of reference data, and control transistors (T1,T2) controlled by an addressing row (L1) for the selective connection of said charge transistors (44,46) to columns (D,D) for the transmission of said (PID) data extracted from the header signal (12);

each memory cell also comprising a set of transistors (T3,T4,T5) assembled as a comparator ensuring the comparison between the data present in the columns (D,D) for the data transmission and the reference data stored in the charge transistors (44,46) so as to deliver, when a reference byte stored in a memory cell row is identical to a byte present in the data transmission columns, a pairing signal (M) to an address coding system (42) connected to the data processing unit (32,34).

3. The device of claim 2, wherein the memory cells are MOS transistor memory cells.

4. The device of claim 2, wherein the associative memory is an associative memory with a storage capacity of 32 bytes of 14 bits.

5. The device of claim 2, further comprising a random-access memory (36) controlled by the data processing unit (32,34) for successive storage in memory of data packets of the same type, in a zone corresponding to the packet type.

6. The device of claim 2, further comprising a means (30) for extracting, from each header signal, bits (29) used for the numbering of the packets of the same type, and for supplying these bits to the data processing unit for the selection of the packets.

7. The device of claim 2, wherein the means for extracting said data from each header signal and said bits used for the numbering of the packets consists of material means (30) for decoding the header signal (12) of each packet.

8. The device of claim 2, wherein the packets (10) of digital data are digital television signal packets which have been transmitted in series at a speed of approximately 60 Mbps.

9. The device of claim 2, wherein the packets (10) of digital data are digital television signal packets which have been transmitted in parallel at a speed of approximately 7.5 Mbps.

10. A digital television signal receiver with each signal consisting of a set of digital data packets, comprising:

decoding means (3,4,5) for decoding the incoming digital signals, adapted to identify said data packets so they can be selected to form trains of packets of the same type and a means for processing said packets (6) adapted so as to generate, from packets of the same type, corresponding analog signals and deliver these analog signals to a device for displaying the video signals and transmitting the acoustic signals (7), wherein that the decoding means comprises;

a means (30) for extracting a portion of data from each header signal, which is representative of the nature of the corresponding useful signal (14);

memory storage means (38,44,46) for the reference data, at addresses each corresponding to one packet type; and

comparison means (T3,T4,T5) for comparing the piece of data extracted from each header signal (12) with said reference data stored in memory and delivering data to a data processing unit (32,34) of an address signal indicating the type of the corresponding packet (10), wherein the memory storage means and the comparison means consist of an associative memory (38) adapted to ensure the simultaneous comparison of the piece of data extracted from each header signal with the reference data stored in memory, wherein the associative memory (38) comprises a network of rows and columns of memory cells each comprising a set of charge transistors (44,46) for the storage of reference data, and control transistors (T1,T2) controlled by an addressing tow (L1) for the selective connection of said charge transistors (44,46) to columns (D,D) for the transmission of said (PID) data extracted from the header signal (12);

each memory cell also comprising a set of transistors (T3,T4,T5) assembled as a comparator ensuring the comparison between the data present in the columns (D,D) for the data transmission and the reference data stored in the charge transistors (44,46) so as to deliver, when a reference byte stored in a memory cell row is identical to a byte present in the data transmission columns, a pairing signal (M) to an address coding system (42) connected to the data processing unit (32,34).