Low leakage electrostatic discharge protection system

• US 6,414,831 B1
• Filed: 02/09/1999
• Issued: 07/02/2002
• Est. Priority Date: 02/21/1998
• Status: Expired due to Fees

• Current Assignee: Zarlink Semiconductor Inc. (Microchip Technology Incorporated)
• Original Assignee: Zarlink Semiconductor Inc. (Microchip Technology Incorporated)
• Inventors: Orchard-Webb, Jonathan Harry
• Primary Examiner(s): Ballato, Josie
• Assistant Examiner(s): HUYNH, KIM NGOC
• Application Number:
  US09/246,842
• Time in Patent Office: 1,239 Days
• Field of Search: 361/54, 361/56, 361/111, 327/309, 327/310, 257/355, 257/356, 257/367
• US Class Current: 361/111
• CPC Class Codes: H01L 27/0255 using diodes as protective elements

Abstract

A protection system employing high voltage input diodes and low voltage supply clamp to prevent input diode leakage increasing due to reverse stress during electrostatic discharge events.

Claims

1. An electrostatic discharge protection circuit suitable for low leakage protection in a CMOS integrated circuit, comprising:

a first high voltage field plated p/n junction diode connected between a positive supply of said circuit and a first input for increasing reverse breakdown voltage of said diode;

a second high voltage field plated p/n junction diode connected between a negative supply of said circuit and said input for increasing reverse breakdown voltage of said diode; and

a third diode connected between said positive supply and said negative supply and having a reverse breakdown voltage exceeding the voltage between said positive supply and said negative supply.

2. The protection circuit as set forth in claim 1, wherein said third diode comprises an npn diode.

3. The protection circuit as set forth in claim 2, wherein said third diode comprises a lateral npn snap back diode.

4. The protection circuit as set forth in claim 1, wherein each diode is a forward bias diode.

5. The protection circuit as set forth in claim 1, wherein said second diode comprises a p-well into an n-substrate.

6. The protection circuit as set forth in claim 1, wherein said first diode comprises an n-well into a p-substrate.

7. The protection circuit as set forth in claim 1, wherein each said diode comprises a Schottky diode.

8. The protection circuit as set forth in claim 1, wherein said third diode comprises a p/n junction diode.

9. The protection circuit as set forth in claim 8, wherein said third diode comprises a high voltage diode.

10. A method of preventing input diode leakage in a CMOS integrated circuit with a positive supply and a negative supply from reverse stress during ESD events, comprising:

providing a first high voltage field plated diode and a second high voltage field plated diode;

connecting said first diode between said positive supply and an input of said circuit;

connecting a third diode between said positive supply and said negative supply, and having a reverse breakdown voltage exceeding the voltage of said first supply and said second supply to substantially prevent diode leakage during ESD events.