nvSRAM with multiple non-volatile memory cells for each SRAM memory cell

• US 6,414,873 B1
• Filed: 03/16/2001
• Issued: 07/02/2002
• Est. Priority Date: 03/16/2001
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Herdt, Christian E.
• Primary Examiner(s): Ho, Hoai V.
• Application Number:
  US09/681,317
• Time in Patent Office: 473 Days
• Field of Search: 365/185.08, 365/185.03, 365/185.05, 365/185.28, 365/185.01, 365/154, 365/129
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor

Abstract

The invention relates to a non-volatile, static random access memory (nvSRAM) in which there are at least two, non-volatile memory cells associated with each SRAM memory cell. The non-volatile memory cells are capable of being programmed with whatever bit of information is present in the SRAM at two different times. In one embodiment, the non-volatile memory cells are capable of being randomly programmed, i.e., programmed in any order. Further, the bits of data programmed into the non-volatile memory cells can be recalled in any order, i.e., randomly recalled.

Claims

1. A non-volatile, static random access memory (nvSRAM) with the ability to store multiple bits of data for each static random access memory cell comprising:

a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining a bit of data, and transmitting a bit of data to the exterior environment;

wherein a bit of data stored in said static random access memory can be lost if power is removed from said static random access memory;

a non-volatile memory, operatively connected to said static random access memory, that includes a first non-volatile memory cell capable of being programmed with a differentially represented bit of data received from said static random access memory and a second nonvolatile memory cell that is also capable of being programmed with a differentially represented bit of data received from said static random access memory;

wherein said first non-volatile memory cell is in series with said second non-volatile memory cell and located between said second non-volatile memory cell and said static random access memory; and

a controller, operatively connected to said static random access memory and said nonvolatile memory, that is capable of causing said non-volatile memory to be programmed with a first differentially represented bit of data stored in said static random access memory at a first time and a second differentially represented bit of data stored in said static random access memory at a second time that is different than said first time.

2. The non-volatile, static random access memory, as claimed in claim 1, wherein:

said controller is capable of causing said first non-volatile memory cell and said second non-volatile memory cell to be programmed with bits of data in any order.

3. The non-volatile, static random access memory, as claimed in claim 1, wherein:

said controller is capable of causing a first bit of data programmed into said first non-volatile memory cell and a second bit of data programmed into said second non-volatile memory cell to be recalled to said static random access memory in any order.

4. The non-volatile, static random access memory, as claimed in claim 1, wherein:

said controller is capable of causing a first bit of data to be transferred to said first non-volatile memory cell before a second bit of data is transferred to said second non-volatile memory cell.

5. The non-volatile, static random access memory, as claimed in claim 1, wherein:

said controller is capable of causing a second bit of data to recalled from said second non-volatile memory cell before a first bit of data is recalled from said first non-volatile memory cell.

6. The non-volatile, static random access memory, as claimed in claim 1, further comprising:

a first switching device, located between said static random access memory and said non-volatile memory, for selectively connecting and disconnecting said static random access memory and said non-volatile memory; and

a second switching device, located between said non-volatile memory and a power supply connection, for selectively connecting and disconnecting said non-volatile memory and a power supply connection.

7. The non-volatile, static random access memory, as claimed in claim 6, wherein:

said controller is capable of using said first and second switches to cause a bit of data to be programmed into one of said first and second non-volatile memory cells with dynamic program inhibit.

8. The non-volatile, static random access memory, as claimed in claim 1, wherein:

said non-volatile memory and said controller are capable of implementing a dynamic program inhibit operation during the programming of a bit of data stored in said static random access memory into either said first non-volatile memory cell or said second non-volatile memory cell.

9. The non-volatile, static random access memory, as claimed in claim 1, wherein:

said non-volatile memory includes more than two non-volatile memory cells connected in series.

10. A non-volatile, static random access memory (nvSRAM) with the ability to store multiple bits of data for each static random access memory cell comprising:

a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining a bit of data, and transmitting a bit of data to the exterior environment;

wherein a bit of data stored in said static random access memory can be lost if power is removed from said static random access memory;

a non-volatile memory, operatively connected to said static random access memory, that includes a first non-volatile memory cell capable of being a dfferentially represented bit of data received from said static random access memory, a second non-volatile memory cell that is also capable of being programmed with a differentially represented bit of data received from said static random access memory;

a first switching device for selectively connecting and disconnecting said static random access memory and said non-volatile memory;

a second switching device for selectively connecting and disconnecting said non-volatile memory and a power supply connection;

wherein said first non-volatile memory cell is in series with said second non-volatile memory cell and located between said second non-volatile memory cell and said static random access memory;

a controller, operatively connected to said static random access memory and said non-volatile memory, that is capable of causing said non-volatile memory to be programmed with a first differentially represented bit of data stored in said static random access memory at a first time and a second differentially represented bit of data stored in said static random access memory at a second time that is different than said first time.

11. The non-volatile, static random access memory, as claimed in claim 10, wherein:

said non-volatile memory and said controller are capable of implementing a dynamic program inhibit operation during the programming of a bit of data stored in said static random access memory into either said first non-volatile memory cell or said second non-volatile memory cell.

12. The non-volatile, static random access memory, as claimed in claim 10, wherein:

said non-volatile memory and said controller are capable of causing said first non-volatile memory cell and said second non-volatile memory cell to be programmed with bits of data in any order.

13. The non-volatile, static random access memory, as claimed in claim 10, wherein:

said non-volatile memory and said controller are capable of causing a first bit of data programmed into said first non-volatile memory cell and a second bit of data programmed into said second non-volatile memory cell to be recalled to said static random access memory in any order.

14. A non-volatile, static random access memory (nvSRAM) with the ability to store multiple bits of data for each static random access memory cell comprising:

a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining a bit of data, and transmitting a bit of data to the exterior environment;

wherein a bit of data stored in said static random access memory can be lost if power is removed from said static random access memory;

a non-volatile memory, operatively connected to said static random access memory, that includes a first non-volatile memory cell capable of being programmed with a differentially represented bit of data received from said static random access memory and a second non-volatile memory cell that is also capable of being programmed with a differentially represented bit of data received from said static random access memory;

an isolation device, located between said static random access memory and said non-volatile memory, to prevent said static random access memory from experiencing a voltage outside the normal voltage range for read and write operations to said static random access memory during a programming of said non-volatile memory;

a controller, operatively connected to said static random access memory and said non-volatile memory, that is capable of causing said non-volatile memory to be programmed with a first differentially represented bit of data stored in said static random access memory at a first time and a second differentially represented bit of data stored in said static random access memory at a second time that is different than said first time.

15. The non-volatile, static random access memory, as claimed in claim 14, wherein:

said first non-volatile memory cell is in series with said second non-volatile memory cell and located between said second non-volatile memory cell and said static random access memory.

16. The non-volatile, static random access memory, as claimed in claim 14, wherein:

said first non-volatile memory cell is in parallel with said second non-volatile memory cell.

17. The non-volatile, static random access memory, as claimed in claim 14, wherein:

said isolation device includes a first switching device, located between said static random access memory and said non-volatile memory, for selectively connecting and disconnecting said static random access memory and said non-volatile memory.

18. The non-volatile, static random access memory, as claimed in claim 14, wherein:

said controller is capable of causing said first non-volatile memory cell and said second non-volatile memory cell to be programmed with bits of data in any order.

19. The non-volatile, static random access memory, as claimed in claim 14, wherein:

said controller is capable of causing a first bit of data programmed into said first non-volatile memory cell and a second bit of data programmed into said second non-volatile memory cell to be recalled to said static random access memory in any order.