Method and apparatus for securing electronic circuits

• US 6,414,884 B1
• Filed: 02/04/2000
• Issued: 07/02/2002
• Est. Priority Date: 02/04/2000
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Sullivan, Paul A., DeFelice, Richard Alden
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US09/498,006
• Time in Patent Office: 879 Days
• Field of Search: 438/130, 438/455, 257/922, 257/777, 257/778, 257/678, 365/53, 365/195, 365/196, 365/52
• US Class Current: 365/195
• CPC Class Codes: G06F 21/86 Secure or tamper-resistant housings
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/57 Protection from inspection, reverse engineering or tampering
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01067 Holmium [Ho]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: Y10S 257/922 with means to prevent inspection of or tampering with an integrated circuit, e.g. "smart card", anti-tamper

Abstract

A method and apparatus for protecting the stored information on an integrated circuit from being compromised through reverse engineering. To do so, the method and apparatus splits the functionality of an integrated circuit into two separate integrated circuits, which are then connected in an interlocking manner. A detection circuit monitors the interconnection of the two separate integrated circuits. Upon detection of a break in the interconnection of the two circuits, the detection circuit destroys the data stored in the two separate integrated circuits. The two integrated circuits are connected in a flip-chip fashion, thereby preventing access to the underlying conduction paths and charge storage sites which are normally used in reverse engineering an integrated circuit.

Claims

1. A method for protecting information contained within an integrated circuit comprising the steps of

splitting the functionality of a circuit-into two separate portions,

implementing the two separate portions as two separate integrated circuits,

interconnecting the two separate integrated circuits in an interlocking manner, and

monitoring an interconnection of the two separate integrated circuits.

2. The method according to claim 1, further comprising the step of destroying the information contained within the two separate integrated circuits upon detecting a break in the interconnection of the two separate integrated circuits.

3. The method according to claim 1, further comprising the step of interconnecting the two separate integrated circuits so that all conduction paths and charge storage sites are not accessible from the exterior.

4. The method according to claim 1, wherein the two separate integrated circuits are connected in a flip-chip manner.

5. The method according to claim 1, further comprising, the step of writing random data to a memory upon detecting a break in the interconnection of the two, separate integrated circuits.

6. The method according to claim 1, further comprising the step of disposing at least a plurality of transistors storing sensitive information under a plurality of bond pads.

7. The method according to claim 1, further comprising the step of disposing at least a plurality of gates storing sensitive information below a plurality of bond pads.

8. An apparatus for storing information comprising:

a first integrated circuit having a plurality of charge storage sites in which charges are stored representing the information to be stored,

a second integrated circuit being coupled to the first integrated circuit in a flip-chip configuration and preventing access to the plurality of charge storage sites,

a detection circuit being disposed in one of the first and second integrated circuits and monitoring a connection between the first and second integrated circuits, said detection circuit altering the information stored in the first integrated circuit upon detecting a break in the connection between the first and second integrated circuits.

9. The apparatus according to claim 8, wherein the second integrated circuit is disposed over only a portion of the first integrated circuit.

10. The apparatus according to claim 8, wherein the first integrated circuit includes a plurality of conduction paths, and said second integrated circuit is coupled to the first integrated circuit so that the first integrated circuit covers the plurality of conduction paths.

11. The apparatus according to claim 8, further comprising a plurality of conduction paths coupling the first integrated circuit to the second integrated circuit, wherein said detection circuit monitors conduction continuity of one or more of the plurality of conduction paths.

12. The apparatus according to claim 8, further comprising a read-write circuit coupled to the detection circuit and the plurality of charge storage sites, said detection circuit enabling said read-write circuit to write false data to the plurality of charge storage sites upon detection of a break in continuity.

13. The apparatus according to claim 8, further comprising an alternate power source being coupled to the detection circuit and providing power to the detection circuit upon removal of normal supply power.

14. The apparatus according to claim 13, wherein the alternate power source also provides power to the read-write circuit upon removal of normal supply power.

15. The apparatus according to claim 13, wherein the alternate power source provides an unsuitable voltage to the plurality of charge storage sites upon detection of a break in the continuity by the detection circuit.

16. The apparatus according to claim 13, wherein the alternate power source includes one or more selected from the group of:

a battery, a capacitor, and an energy storage device.

17. The apparatus according to claim 13, wherein the alternate power source includes a plurality of capacitors coupled in a parallel configuration during charging, and switched to a series configuration upon detection of a continuity fault.

18. An apparatus for storing information comprising:

a first integrated circuit having a plurality of charge storage sites in which charges are stored representing the information to be stored,

a second integrated circuit being coupled to the first integrated circuit in a flip-chip configuration and preventing access to the plurality of charge storage sites,

a proximity detection circuit being disposed in one of the first and second integrated circuits and monitoring a proximity of the first integrated circuit relative to the second integrate circuit, said proximity detection circuit altering the information stored in the first integrated circuit upon detecting a change in the proximity between the first and second integrated circuits.

19. The apparatus according to claim 18, wherein the second integrated circuit is disposed over only a portion of the first integrated circuit.

20. The apparatus according to claim 18, wherein the first integrated circuit includes a plurality of conduction paths, and said second integrated circuit is coupled to the first integrated circuit so that the first integrated circuit covers the plurality of conduction paths.

21. The apparatus according to claim 18, further comprising a read-write circuit coupled to the proximity detection circuit and the plurality of charge storage sites, said proximity detection circuit enabling said read-write circuit to write false data to the plurality of charge storage sites upon detection of a change in the proximity between the first and second integrated circuits.

22. The apparatus according to claim 18, further comprising an alternate power source being coupled to the proximity detection circuit and providing power, to the detection circuit upon removal of normal supply power.

23. The apparatus according to claim 22, wherein the alternate power source also provides power to the read-write circuit upon removal of normal supply power.

24. The apparatus according to claim 22, wherein the alternate power source provides an unsuitable voltage to the plurality of charge storage sites upon detection of a change in the proximity between the first and second integrated circuits.

25. The apparatus according to claim 22, wherein the alternate power source includes one or more selected from the group of:

a battery, a capacitor, and an energy storage device.