Integrated memory with interblock redundancy

• US 6,414,886 B2
• Filed: 02/12/2001
• Issued: 07/02/2002
• Est. Priority Date: 08/12/1998
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Wu, Xiaofeng, Täuber, Andreas
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/781,175
• Publication Number:
  US 20010015921A1
• Time in Patent Office: 505 Days
• Field of Search: 365/200, 365/230.01, 365/230.03, 365/230.06
• US Class Current: 365/200
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme

Abstract

An integrated memory is described that has memory blocks with column lines and row lines as well as at least one redundancy row line for replacing in each case one of the row lines in any of the memory blocks. In addition, each memory and memory block has a deactivation unit for deactivating the memory block. The integrated memory has deactivation lines, each of which is connected to an input of the deactivation unit of one of the memory blocks. Each memory block has a deactivation decoder that is connected at the output end to all the deactivation lines. If one of the row lines of a first memory block of the memory blocks is replaced by a redundancy row line of a second memory block of the memory blocks, the deactivation decoder of the second memory block deactivates the first memory block via the corresponding deactivation line.

Claims

1. An integrated memory, comprising:

deactivation lines; and

memory blocks including a first memory block and a second memory block, each of said memory blocks containing;

row lines;

column lines intersecting said row lines at intersection point;

memory cells disposed at said intersection points of said column lines and said row lines;

at least one redundancy row line for replacing and intersection a respective one of said row lines;

a deactivation unit for deactivating said first memory block and having an input and an output, said input connected to one of said deactivation lines; and

a deactivation decoder having an output end connected to said deactivation lines assigned to said second memory block, if one of said row lines of said first memory block of said memory blocks is replaced by said redundancy row line of said second memory block of said memory blocks, said deactivation decoder deactivates said first memory block through a corresponding one of said deactivation lines.

2. The integrated memory according to claim 1,

including an address bus connected to said memory blocks, said address bus transmitting block addresses and row addresses;

wherein said memory blocks each have at least one redundancy memory unit for storing a block address and a row address of one of said row lines which is to replaced by said redundancy row line of one of said memory blocks;

wherein said memory blocks each have a comparator unit connected to said redundancy memory unit, said comparator unit having a result output and compares an address transmitted through said address bus with the address stored in said redundancy memory unit, which, given correspondence, generates a result signal available at said result output; and

wherein said deactivation decoder having a first input connected to said redundancy memory unit for supplying the block address of said row line which is to be replaced, and a second input connected to said result output of said comparator unit, and, if the result signal is activated, said deactivation decoder deactivates, through a corresponding one of said deactivation lines a respective one of said memory blocks whose block address is supplied to it from said redundancy memory unit.

3. The integrated memory according to claim 2, wherein

the block address is encoded with n address bits;

at least two of said memory blocks can be addressed using common block group addresses which are encoded with m<

n of the address bits which are parts of the block address;

said comparator unit compares the address stored in said redundancy memory unit with the common block group address present on the address bus and the row address; and

said deactivation decoder is supplied with the block address of said respective one of said memory blocks whose row line is to be replaced.

4. The integrated memory according to claim 1, wherein said column lines are bit lines, and said row lines are word lines.

5. The integrated memory according to claim 1, wherein said column lines are word lines and said row lines are bit lines.