System, method and apparatus for an instruction driven digital video processor

• US 6,414,996 B1
• Filed: 12/08/1998
• Issued: 07/02/2002
• Est. Priority Date: 12/08/1998
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: McDade, Darryn, Owen, Jefferson Eugene
• Primary Examiner(s): Le, Vu
• Application Number:
  US09/207,343
• Time in Patent Office: 1,302 Days
• Field of Search: 375/240.16, 375/240.17, 375/240.25, 375/240.26, 348/402.1, 348/407.1, 348/413.1, 348/416.1, 348/699-700, 382/236
• US Class Current: 375/240.17
• CPC Class Codes: H04N 19/523 with sub-pixel accuracy

Abstract

The present invention provides a system, method and an apparatus for a digital video processor comprising an error memory and a merge memory, a half pixel filter communicably coupled to the merge memory, a controller communicably coupled to the error memory, the merge memory and the half pixel filter. The present invention also including a sum unit communicably coupled to the error memory. The controller executing one or more instructions to provide motion compensation during video decoding.

Claims

1. A digital video processor comprising:

an error memory and a merge memory;

a half pixel filter communicably coupled to the merge memory;

a controller communicably coupled to the error memory, the merge memory and the half pixel filter, the controller executing one or more instructions to provide motion compensation during video decoding; and

a sum unit communicably coupled to the error memory and the merge memory.

2. The digital video processor as recited in claim 1, wherein the half pixel filter is programmable.

3. The digital video processor as recited in claim 1, wherein the error memory and the merge memory are random access memory.

4. The digital video processor as recited in claim 1, further comprising:

an error buffer communicably coupled to the error memory;

an instruction buffer communicably coupled to the controller;

a reference buffer communicably coupled to the half pixel filter; and

a display buffer communicably coupled to the sum unit.

5. The digital video processor as recited in claim 4, wherein the error buffer, the instruction buffer, the reference buffer and the display buffer are random access memory.

6. The digital video processor as recited in claim 1, wherein the one or more instructions includes at least one of a load instruction, a merge instruction and a write instruction.

7. The digital video processor as recited in claim 1, wherein the controller further comprises:

an instruction queue;

an execution unit communicably connected to the instruction queue and the error memory; and

a motion compensation state machine communicably connected to the execution unit, the half pixel filter and the merge memory.

8. The digital video processor as recited in claim 1, wherein the sum unit utilizes at least one or more error terms stored in the error memory with one or more filtered prediction blocks stored in the merge memory to produce a decoded macroblock.

9. The digital video processor as recited in claim 1, wherein the half pixel filter performs vertical and horizontal half-pixel interpolation on a block as dictated by a motion vector.

10. A digital video processor comprising:

an error memory configured to store one or more error terms;

a merge memory configured to store one or more filtered prediction blocks;

a filter communicably coupled to the merge memory, the filter configured to perform vertical and horizontal half-pixel interpolation on a block as dictated by a motion vector;

an instruction queue configured to store one or more instructions;

an execution unit communicably coupled to the instruction queue and the error memory, the execution unit configured to receive an instruction from the instruction queue, determine whether the error memory is full and send the instruction to a motion compensation state machine for execution;

the motion compensation state machine communicably coupled to the execution unit, the filter and the merge memory, the motion compensation state machine configured to execute the instruction received from the execution unit; and

a sum unit communicably coupled to the error memory and the merge memory, the sum unit utilizes at least one or more error terms stored in the error memory with one or more filtered prediction blocks stored in the merge memory to produce a decoded macroblock.

11. The digital video processor as recited in claim 10, wherein the filter and the motion compensation state machine are programmable.

12. The digital video processor as recited in claim 10, further comprising:

an error buffer communicably coupled to the error memory;

an instruction buffer communicably coupled to the controller;

a reference buffer communicably coupled to the half pixel filter; and

a display buffer communicably coupled to the sum unit.

13. The digital video processor as recited in claim 10, wherein the motion compensation state machine is further configured to execute a load instruction, a merge instruction or a write instruction.

14. A digital video processor comprising:

an error buffer;

an error memory communicably coupled to the error buffer, the error memory configured to receive and store one or more error terms from the error buffer;

an instruction buffer;

an instruction queue communicably coupled to the instruction buffer, the instruction queue configured to receive and store one or more instructions from the instruction buffer;

merge memory configured to receive and store one or more filtered prediction blocks;

a reference buffer;

a half pixel filter communicably coupled to the reference buffer and the merge memory, the half pixel filter performing vertical and horizontal half-pixel interpolation on a prediction block received from the reference buffer as dictated by a motion vector to produce a filtered prediction block, and writing the filtered prediction block to the merge memory;

an execution unit communicably coupled to the instruction queue and the error memory, the execution unit configured to receive an instruction from the instruction queue, determine whether the error memory is full and send the instruction to a motion compensation state machine for execution;

the motion compensation state machine communicably coupled to the execution unit, the half pixel filter and the merge memory, the motion compensation state machine configured to execute the instruction received from the execution unit; and

a sum unit communicably coupled to the error memory and the merge memory, the sum unit utilizing at least one or more error terms stored in the error memory and one or more filtered prediction blocks stored in the merge memory to produce a decoded macroblock, and to write the decoded macroblock to an display buffer.

15. The digital video processor as recited in claim 14, wherein the half pixel filter and the motion compensation state machine are programmable.