Memory device having a plurality of programmable internal registers and a delay time register

• US 6,415,339 B1
• Filed: 12/28/1998
• Issued: 07/02/2002
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Cao, Chun
• Application Number:
  US09/221,108
• Time in Patent Office: 1,282 Days
• Field of Search: 365/194, 365/230.01, 710/3, 710/23, 710/26, 710/36, 710/104, 710/130
• US Class Current: 710/23
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A synchronous memory device and a method of controlling the memory device. The memory device including at least one memory section having a plurality of memory cells. The memory device includes a first internal register to store a value which is indicative of a number of clock cycles to transpire before the memory device responds to a read request. The memory device also includes a second internal register to store an identification value to identify the memory device on a bus.

Claims

1. A synchronous memory device, wherein the memory device includes at least one memory section having a plurality of memory cells, the memory device comprises:

a first internal register to store a value which is indicative of a number of clock cycles to transpire before the memory device responds to a read request; and

a second internal register to store an identification value to identify the memory device on a bus.

2. The memory device of claim 1 wherein the second internal register stores a unique identification value to identify the memory device from a plurality of other memory devices on the bus.

3. The memory device of claim 1 wherein the second internal register stores a special identification value to identify the memory device and a plurality of other memory devices on the bus.

4. The memory device of claim 1 further including a third internal register to store information indicative of a type of memory device.

5. The memory device of claim 1 further including a third internal register to store information indicative of a density of the memory device.

6. The memory device of claim 1 further including an address register to store information indicative of a range of bus addresses assigned to the memory device.

7. The memory device of claim 1 further including an address register to store information indicative of a range of bus addresses to which the memory device is responsive to.

8. The memory device of claim 1 further including comparison circuitry to receive a transaction request and determine whether the transaction request includes a field which corresponds to the identification value wherein, the memory device responds to the transaction request when the field corresponds to the identification value.

9. The memory device of claim 1 wherein the first internal register is programmable.

10. The memory device of claim 9 wherein the second internal register is programmable.

11. The memory device of claim 10 wherein the first and second internal registers are programmed after power is applied to the memory device or during initialization of the memory device.

12. A synchronous memory device having at least one memory section which includes a plurality of memory cells, the memory device comprises:

a latency register to store a value which is representative of a number of clock cycles to transpire before the memory device responds to a read request;

an internal identification register to store an identification value which identifies the memory device on a bus containing a plurality of memory devices;

clock receiver circuitry to receive at least one external clock signal; and

an output driver to output data on to the bus in accordance with the value stored in the latency register and synchronously with respect to the external clock signal.

13. The memory device of claim 12 further including a device interface to electrically couple the memory device to the bus wherein the device interface device receives and interprets a transaction request when the identification information in the transaction request corresponds to identification value in the internal identification register.

14. The semiconductor device of claim 12 further including internal clock generation circuitry to generate a first internal clock signal using a delay locked loop and the external clock signal.

15. The memory device of claim 12 wherein the clock receiver circuitry receives two external clock signals and wherein the memory device further includes internal clock generation circuitry to generate a first internal clock signal using a delay locked loop and the two external clock signals.

16. The memory device of claim 15 wherein the two external clock signals are substantially complementary of each other.

17. The memory device of claim 12 wherein the internal identification register stores a unique identification value to precisely identify the memory device from the plurality of memory devices on the bus.

18. The memory device of claim 12 wherein the internal identification register stores a special identification value to identify the memory device and the plurality of memory devices on the bus.

19. The memory device of claim 12 further including an address register to store information indicative of a range of bus addresses assigned to the memory device.

20. The memory device of claim 12 wherein the latency register and the internal identification register are programmable.

21. A method of controlling a semiconductor memory device, the method comprising:

storing a latency value in a first programmable register, the latency value being representative of a number of clock cycles which are to transpire before the memory device responds to a read request; and

storing a device identification value in a second programmable register wherein the device identification value uniquely identifies the memory device from a plurality of memory devices on a bus.

22. The method of claim 21 further including issuing a set register request wherein, in response to the set register request, the memory device stores a latency value in the first programmable register.

23. The method of claim 21 wherein the memory device stores the device identification value in the second programmable register after power is applied to the device or during the initialization.

24. The method of claim 21 further including the step of driving data onto the bus, in response to a read request, at a time depending on the latency value stored in the first programable register.

25. The method of claim 21 further including the step of driving data onto the bus, in response to a read request, wherein the data is driven onto the bus synchronously with respect to a first external clock signal and in accordance with the latency value stored in the first programmable register.

26. The method of claim 24 further including the step of driving data onto the bus, in response to a read request, wherein the data is driven onto the bus synchronously with respect to a first and a second external clock signal and in accordance with the latency value stored in the first programmable register.