Disk drive with unified channel-disk controller bus for transmitting user data, servo data, and register data

• US 6,415,349 B1
• Filed: 01/24/2000
• Issued: 07/02/2002
• Est. Priority Date: 01/24/2000
• Status: Expired due to Term

• Current Assignee: Western Digital Corporation
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Hull, Richard W., Jung, Hoover K., Mathur, Sanjay S.
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): GOODARZI, NASSER MOAZZAMI
• Application Number:
  US09/489,856
• Time in Patent Office: 890 Days
• Field of Search: 711/112, 711/100, 711/111, 360/39-77
• US Class Current: 711/100
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals

Abstract

A disk drive has a unified bus forming a signal path for transmitting register data, user data and servo sectors. The unified bus is connected between a channel circuit and a disk controller circuit. The channel circuit has an output stream engine which responds to and provides control signals to multiplex data on the unified bus at various times between demodulated user data, servo sector data and register data.

Claims

1. A disk drive comprising:

a disk comprising a track having a data sector and a servo sector;

a channel circuit;

a disk controller circuit;

a unified bus connected between the channel circuit and the disk controller circuit and having a data-carrying medium;

the channel circuit comprising;

a channel register for storing register data;

means for receiving and demodulating a first series of signals representing data stored in the servo sector to create a first demodulated series of signals;

means for receiving and demodulating a second series of signals representing data stored in at least a portion of the data sector to create a second demodulated series of signals;

a channel output stream engine coupled to the unified bus for transmitting and receiving the register data and for transmitting the first and second demodulated series of signals on the data-carrying medium;

wherein during a first interval the data-carrying medium reflects the register data, during a second interval the data-carrying medium reflects the first demodulated series of signals, and during a third interval the data-carrying medium reflects the second demodulated series of signals.

2. The disk drive of claim 1, wherein the disk controller circuit includes means for timing the receiving of the first and second series of signals.

3. The disk drive of claim 2, wherein the unified bus includes a read gate signal.

4. The disk drive of claim 3, wherein the disk controller circuit asserts the read gate signal when it is time for the channel circuit to receive the second series of signals.

5. The disk drive of claim 2, wherein the unified bus further comprises a servo gate signal.

6. The disk drive of claim 5, wherein the disk controller circuit asserts the servo gate signal when it is time for the channel circuit to receive the first series of signals.

7. The disk drive of claim 1 wherein the second series of signals are demodulated and transmitted with longer latency than the first series of signals.

8. The disk drive of claim 1, wherein the unified bus further comprises a data valid signal.

9. The disk drive of claim 8, wherein the channel circuit asserts the data valid signal for transmitting each of the first and second demodulated series of signals.

10. The disk drive of claim 9, wherein the first demodulated series of signals is transmitted in a plurality of servo data packets, wherein each servo data packet includes an identification header.

11. The disk drive of claim 10, wherein the channel circuit asserts the data valid signal at the beginning of transmitting each servo data packet and de-asserts the data valid signal at the end of transmitting each servo data packet during the second interval.

12. The disk drive of claim 1, further comprising a microprocessor and a microprocessor bus connecting the microprocessor to the disk controller circuit, wherein the microprocessor transmits control commands to the disk controller circuit.

13. The disk drive of claim 12, wherein the disk controller circuit further comprises a register data image for storing the register data.

14. The disk drive of claim 13, wherein the microprocessor transmits control commands to the disk controller circuit to enable the disk controller circuit to transmit the register data on the unified bus during the first interval.

15. The disk drive of claim 14, wherein the disk-controller bus further comprises an address latch enable chip select signal (ALE/CSEL).

16. The disk drive of claim 15, wherein the disk controller circuit is further for asserting the ALE/CSEL at the beginning of the first interval and for de-asserting the ALE/CSEL at the end of the first interval.

17. The disk drive of claim 1, wherein the unified bus further comprises a write gate signal.

18. The disk drive of claim 17, wherein the disk controller circuit asserts the write gate signal during a fourth interval wherein a third series of signals comprising write data are transmitted from the disk controller circuit to the channel circuit during the fourth interval.

19. The disk drive of claim 1, wherein the channel circuit transmits a data header signal for identifying the second series of signals before transmitting the second series of signals.

20. The disk drive of claim 1 wherein the data-carrying medium is a serial bus.

21. The disk drive of claim 1 wherein the data-carrying medium is a parallel bus.