Minimizing self-modifying code checks for uncacheable memory types

• US 6,415,360 B1
• Filed: 05/18/1999
• Issued: 07/02/2002
• Est. Priority Date: 05/18/1999
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lewchuk, William Kurt, Hughes, William Alexander, Zuraski, Gerald D. Jr.
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): Vital, Pierre M.
• Application Number:
  US09/314,066
• Time in Patent Office: 1,141 Days
• Field of Search: 711/138, 711/139, 711/118, 711/125, 711/126
• US Class Current: 711/139
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 9/3812 with instruction modification, e.g. store into instruction stream

Abstract

A processor employs an SMC check apparatus. The SMC check apparatus may minimize the number of explicit SMC checks performed for non-cacheable stores. Cacheable stores may be handled using any suitable mechanism. For non-cacheable stores, the processor tracks whether or not the in-flight instructions are cached. Upon encountering a non-cacheable store, the processor inhibits an SMC check if the in-flight instructions are cached. Since, for performance reasons, the code stream is often cached, non-cacheable stores may frequently be able to skip an explicit, complex, and time consuming SMC check. Performance of non-cacheable stores (and memory throughput overall) may be increased. The handling of non-cacheable stores as described herein may be particularly beneficial to video data manipulations, which may frequently be of a non-cacheable memory type and which may be important to the overall performance of a computer system.

Claims

1. A processor comprising:

a load/store unit including;

a buffer configured to store a store memory operation and a corresponding cacheability indication; and

a control logic configured to set said cacheability indication according to a translation of a store address corresponding to said store memory operation, and wherein said control logic is coupled to receive a signal indicative of whether one or more instructions in-flight within said processor are uncacheable, and wherein said control logic is configured to inhibit a self-modifying code (SMC) check for said store memory operation responsive to;

(i) said cacheability indication indicating non-cacheable; and

(ii) said signal indicating cacheable.

2. The processor as recited in claim 1 wherein said control logic is configured to initiate said SMC check for said store memory operation responsive to:

(i) said cacheability indication indicating non-cacheable; and

(ii) said signal indicating uncacheable.

3. The processor as recited in claim 1 further comprising an instruction cache configured to generate said signal.

4. The processor as recited in claim 3 wherein said instruction cache comprises a second buffer configured to store instruction addresses of instructions in-flight within said processor.

5. The processor as recited in claim 4 wherein said second buffer is configured to store said addresses on a fetch block basis.

6. The processor as recited in claim 4 wherein said second buffer is configured to store a cache state for each instruction address.

7. The processor as recited in claim 6 wherein said state comprises prefetch buffer, cached, and not-cached.

8. The processor as recited in claim 7 wherein said instruction cache is configured to assert said signal to indicate uncacheable if a state corresponding to any instruction address within said second buffer comprises not-cached.

9. The processor as recited in claim 4 wherein each of said instruction addresses is logged into said second buffer in response to a fetch of one or more instructions at said each of said instruction addresses from said instruction cache.

10. The processor as recited in claim 9 further comprising a reorder buffer, wherein said each of said addresses is deleted upon retirement, from said reorder buffer, of each of said one or more instructions.

11. The processor as recited in claim 1 further comprising a reorder buffer, wherein said reorder buffer is configured to convey an indication to said load/store unit that said store memory operation is retirable, and wherein said load/store unit is configured to initiate said SMC check in response to said indication.

12. The processor as recited in claim 11 wherein said load/store unit is configured to return a synchronization indication to said reorder buffer if said SMC check indicates a match between a store address corresponding to said store memory operation and an instruction address of one or more instructions in-flight within said processor.

13. The processor as recited in claim 12 wherein said reorder buffer is configured, in response to said synchronization indication, to purge instructions subsequent to an instruction corresponding to said store memory operation and to refetch purged instructions subsequent to said store memory operation committing to said data cache.

14. A computer system comprising:

a processor including;

a load/store unit including (i) a buffer configured to store a store memory operation and a corresponding cacheability indication; and

(ii) a control logic configured to set said cacheability indication according to a translation of a store address corresponding to said store memory operation, and wherein said control logic is coupled to receive a signal indicative of whether one or more instructions in-flight within said processor are uncacheable, and wherein said control logic is configured to inhibit a self-modifying code (SMC) check for said store memory operation responsive to;

(i) said cacheability indication indicating non-cacheable; and

(ii) said signal indicating cacheable; and

a peripheral device for providing communication between said computer system and another computer system to which said peripheral device is coupled.

15. The computer system as recited in claim 14 wherein said peripheral device comprises a modem.

16. The computer system as recited in claim 14 further comprising a second processor coupled in parallel with said processor.

17. A method for performing self-modifying code (SMC) checks in a processor, the method comprising:

determining that a store memory operation is non-cacheable;

asserting a signal if one or more instructions in-flight within said processor are non-cacheable; and

inhibiting an SMC check for said store memory operation if said store memory operation is non-cacheable and said signal is deasserted.

18. The method as recited in claim 17 further comprising initiating said SMC check if said store memory operation is non-cacheable and said signal is asserted.

19. The method as recited in claim 17 further comprising synchronizing subsequent to said store memory operation if said SMC check indicates a match between a store address corresponding to said store memory operation and an instruction address of one or more instructions in-flight within said processor.

20. An apparatus comprising:

a buffer configured to store a store memory operation and a corresponding cacheability indication; and

a control logic coupled to the buffer and to receive a signal indicative of whether one or more instructions in-flight within said processor are uncacheable, and wherein said control logic is configured to inhibit a self-modifying code (SMC) check for said store memory operation responsive to;

(i) said cacheability indication indicating non-cacheable; and

(ii) said signal indicating cacheable.

21. The apparatus as recited in claim 20 wherein the control logic is further configured to set said cacheability indication according to a translation of a store address corresponding to said store memory operation.

22. The apparatus as recited in claim 20 wherein said control logic is configured to initiate said SMC check for said store memory operation responsive to:

(i) said cacheability indication indicating non-cacheable; and

(ii) said signal indicating uncacheable.

23. The apparatus as recited in claim 20 further comprising a second buffer configured to store instruction addresses of instructions in-flight within said processor.

24. The apparatus as recited in claim 23 wherein said second buffer is configured to store said addresses on a fetch block basis.

25. The apparatus as recited in claim 23 wherein said second buffer is configured to store a cache state for each instruction address.

26. The apparatus as recited in claim 25 wherein said state comprises one of at least cached and not-cached.

27. The apparatus as recited in claim 26 further comprising a second control logic coupled to the second buffer, wherein said second control logic is configured to assert said signal to indicate uncacheable if a state corresponding to any instruction address within said second buffer comprises not-cached.

28. The apparatus as recited in claim 27 wherein each of said instruction addresses is logged into said second buffer in response to a fetch of one or more instructions at said each of said instruction addresses from an instruction cache.

29. The apparatus as recited in claim 28 further comprising a reorder buffer, wherein said each of said addresses is deleted upon retirement, from said reorder buffer, of each of said one or more instructions.

30. The apparatus as recited in claim 20 further comprising a reorder buffer, wherein said reorder buffer is configured to convey an indication to said control logic that said store memory operation is retirable, and wherein said control logic is configured to initiate said SMC check in response to said indication.

31. The apparatus as recited in claim 30 wherein said control logic is configured to return a synchronization indication to said reorder buffer if said SMC check indicates a match between a store address corresponding to said store memory operation and an instruction address of one or more instructions in-flight within said processor.

32. The apparatus as recited in claim 31 wherein said reorder buffer is configured, in response to said synchronization indication, to purge instructions subsequent to an instruction corresponding to said store memory operation and to refetch purged instructions subsequent to said store memory operation committing.

33. A method for performing self-modifying code (SMC) checks in a processor, the method comprising:

determining that a store memory operation is non-cacheable;

determining whether or not one or more in-flight instructions are non-cacheable; and

inhibiting an SMC check for said store memory operation if said store memory operation is non-cacheable and said in-flight instructions are cacheable.

34. The method as recited in claim 33 further comprising initiating said SMC check if said store memory operation is non-cacheable and at least one of said in-flight instructions are non-cacheable.

35. The method as recited in claim 34 further comprising synchronizing subsequent to said store memory operation if said SMC check indicates a match between a store address corresponding to said store memory operation and an instruction address of one or more of said in-flight instructions.