Method and circuit for analysis of the operation of a microcontroller using signature analysis during operation

• US 6,415,394 B1
• Filed: 05/10/1999
• Issued: 07/02/2002
• Est. Priority Date: 05/10/1999
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Delphi Technologies, Inc. (BorgWarner Incorporated)
• Inventors: Fruehling, Terry L., Duncan, Charles I., Helm, Troy L.
• Primary Examiner(s): Beausoleil, Robert
• Assistant Examiner(s): Wilson, Yolanda L.
• Application Number:
  US09/309,054
• Time in Patent Office: 1,149 Days
• Field of Search: 714/736, 714/732, 714/25, 714/30, 714/32, 714/45, 714/48
• US Class Current: 714/30
• CPC Class Codes: G06F 11/27 Built-in tests

Abstract

A method and circuit for determining the health of a microcontroller is provided having a circuit that includes a bus having data streams thereon. A first CPU is coupled to the bus. A linear feedback shift register is coupled to the bus and generates a signature in response to the data streams. A memory is coupled to the bus. The memory is utilized by the first CPU. A controller is coupled to the register for controlling the reading of the data streams. The register generates a second signature in response to the data stream. The controller compares the reference signature and the second signature. The controller generates a fault signal when the reference signature is unequal to the second signature.

Claims

1. A circuit comprising:

a bus having data streams thereon;

a first CPU coupled to the bus;

a linear feedback shift register coupled to the bus;

a memory coupled to the bus, said memory storing a reference signature; and

a controller coupled to the register for controlling reading of said data streams, said register generating a second signature in response to said data streams, said controller comparing said reference signature and said second signature, said controller generating a fault signal when the reference signature is unequal to the second signature, wherein said register is comprised of a first data register coupled to said bus, and a control register coupled to said bus.

2. A circuit as recited in claim 1 further comprising a total cycle counter coupled to a bus control logic.

3. A circuit as recited in claim 1 further comprising a second data register coupled to said bus.

4. A circuit as recited in claim 3 further comprising a plurality of feedback register stages coupled to said first data register, said second data register and said control register.

5. A circuit comprising:

a bus having data streams thereon;

a first CPU coupled to the bus;

a linear feedback shift register coupled to the bus;

a memory coupled to the bus, said memory storing a reference signature;

a controller coupled to the register for controlling reading of said data streams, said register generating a second signature in response to said data streams, said controller comparing said reference signature and said second signature, said controller generating a fault signal when the reference signature is unequal to the second signature; and

,

a second CPU coupled to the bus, said second CPU concurrently utilizing said memory with said first CPU.

6. A circuit comprising:

a bus having data streams thereon;

a first CPU coupled to the bus;

a linear feedback shift register coupled to the bus;

a memory coupled to the bus, said memory storing a reference signature; and

a controller coupled to the register for controlling reading of said data streams, said register generating a second signature in response to said data streams, said controller comparing said reference signature and said second signature, said controller generating a fault signal when the reference signature is unequal to the second signature; and

,

an isolation gate coupled to said bus between said first CPU and said second CPU.

7. A circuit, comprising:

a bus having a control line having instructions thereon, and a data bus having data thereon;

a linear feedback shift register coupled to said bus, said linear feedback shift register generating a signature in response to said data;

a bus control logic circuit coupled to the control and coupled to the shift register for controlling reading of said data streams, said control logic circuit comparing said reference signature and said second signature, said controller generating a fault signal when the reference signature is unequal to the second signature, wherein said register is comprised of a first data register coupled to said bus, and a control register coupled to said bus.

8. A circuit as recited in claim 7 further comprising a total cycle counter coupled to the bus control logic.

9. A circuit as recited in claim 7 further comprising a second data register coupled to said bus.

10. A circuit as recited in claim 9 further comprising a plurality of feedback register stages coupled to said first data register, said second data register and said control register.

11. A circuit comprising:

a bus having a control line having instructions thereon, and a data bus having data thereon;

a linear feedback shift register coupled to said bus, said linear feedback shift register generating a signature in response to said data;

a bus control logic circuit coupled to the control and coupled to the shift register for controlling reading of said data streams, said control logic circuit comparing said reference signature and said second signature, said controller generating a fault signal when the reference signature is unequal to the second signature; and

,

an isolation gate coupled to said bus between said first CPU and said second CPU.

12. A method of validating the operation of an operating microcontroller unit, comprising the steps of:

executing an algorithm in a CPU within the microcontroller;

obtaining data bus contents during the operation of the CPU in foreground mode;

loading data bus contents into a linear feedback shift register;

generating a second signature in response to the data;

comparing the reference signature to the second signature to obtain a comparison; and

,

indicating a fault in response to the comparison; and

,

executing an interrupt service routine to obtain an operating signature.

13. A method of validating the operation of an operating microcontroller unit, comprising the steps of:

executing an algorithm in a CPU within the microcontroller;

obtaining data bus contents during the operation of the CPU in foreground mode;

loading data bus contents into a linear feedback shift register;

generating a second signature in response to the data;

comparing the reference signature to the second signature to obtain a comparison; and

,

indicating a fault in response to the comparison; and

,

polling a signature interrupt flag bit during each control cycle;

monitoring a transition of a signature control bit;

when the signature control bit indicates an operating signature is complete, comparing the reference operating signature to the operating signature; and

indicating a fault.