Integrated verification and manufacturability tool

• US 6,415,421 B2
• Filed: 12/22/2000
• Issued: 07/02/2002
• Est. Priority Date: 06/13/2000
• Status: Expired due to Term

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Cobb, Nicolas B., Grodd, Laurence W., You, Siqiong, Anderson, Leigh C., Sahouria, Emile
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US09/747,190
• Publication Number:
  US 20010052107A1
• Time in Patent Office: 557 Days
• Field of Search: 716/4, 716/5, 716/19, 716/20, 716/21
• US Class Current: 716/52
• CPC Class Codes: G03F 1/26 Phase shift masks [PSM]; PSM blanks; Preparation thereof
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.

Claims

1. An integrated verification and manufacturability tool comprising:

a hierarchical database to represent at least a portion of an integrated device layout in a hierarchical manner;

a checking component to operate on the integrated device design by accessing said database; and

an optical process correction (OPC) component to operate on the integrated device layout by accessing said database.

2. The integrated verification and manufacturability tool of claim 1, wherein the checking component comprises a layout versus schematic (LVS) component.

3. The integrated verification and manufacturability tool of claim 1, wherein the checking component comprises a design rule checking (DRC) component.

4. The integrated verification and manufacturability tool of claim 1, further comprising a phase shift mask (PSM) component.

5. The integrated verification and manufacturability tool of claim 1, further comprising an optical rule checking (ORC) component.

6. The integrated verification and manufacturability tool of claim 1, wherein the OPC component and the checking component operate on sets of edges that represent a portion of the integrated device layout.

7. The integrated verification and manufacturability tool of claim 1, wherein the integrated device layout is an integrated circuit (IC) layout.

8. The integrated verification and manufacturability tool of claim 1, wherein the hierarchical database includes one or more intermediate layers.

9. The integrated verification and manufacturability tool of claim 8, wherein a number of intermediate layers to be included in the hierarchical database is determined based, at least in part, on operations to be performed on the integrated device layout.

10. A method comprising:

importing an integrated device layout into a common hierarchical database to create shared data;

executing a sequence of program instructions that initiate the operation of one or more checking components that perform layout verification operations on the shared data; and

executing a sequence of program instructions that initiate the operation of a distinct optical process correction component that performs optical process correction (OPC) operations on the shared data.

11. The method of claim 10, wherein the one or more checking components include a component that performs layout versus schematic (LVS) operations on the shared data.

12. The method of claim 10, wherein the one or more checking components include a component that performs design rule checking (DRC) operations on the shared data.

13. The method of claim 10, wherein the one or more checking components include a component that performs design rule checking (DRC) operations on simulated silicon edges within the shared data.

14. The method of claim 10, further comprising executing a sequence of program instructions that initiate the operation of a component that performs phase shift mask (PSM) operations on the shared data.

15. The method of claim 10, further comprising executing a sequence of program instructions that initiate the operation of a distinct component that performs optical rule checking (ORC) operations on the shared data.

16. The method of claim 10, wherein importing an integrated device layout into the hierarchical database comprises analyzing an original integrated device layout for redundant patterns and replacing one or more of the redundant patterns with cells that include the redundant patterns.

17. The method of claim 10, wherein importing an integrated device layout into the hierarchical database comprises converting one or more portions of the layout comprising a single layer to one or more portions of the layout comprising multi-level hierarchical layouts.

18. The method of claim 10, wherein the layout verification operations and the optical process correction (OPC) operations are performed on a set of edges that represent portions of the integrated device layout within the shared data.

19. The method of claim 10, wherein the integrated device layout comprises an integrated circuit (IC) layout.

20. A machine-readable medium having stored thereon sequences of instructions that, when executed, cause one or more electronic systems to:

import an integrated device layout to a common hierarchical database to create shared data;

initiate the operation of one or more checking components that perform layout verification operations on the integrated device design on the shared data; and

initiate the operation of a distinct optical process correction component that performs optical process correction (OPC) operations on the shared data.

21. The machine-readable medium of claim 20, wherein the one or more checking components perform layout versus schematic (LVS) operations on the shared data.

22. The machine-readable medium of claim 20, wherein the one or more checking components perform design rule checking (DRC) operations on the shared data.

23. The machine-readable medium of claim 20, further comprising sequences of instructions that, when executed, cause the one or more electronic systems to initiate the operation of a component that performs phase shift mask (PSM) operations on the shared data.

24. The machine-readable medium of claim 20, further comprising sequences of instructions that, when executed, cause the one or more electronic systems to initiate the operation of a component that performs optical rule checking (ORC) operations on the shared data.

25. The machine-readable medium of claim 20, further comprising sequences of instructions that, when executed, cause the one or more electronic systems to initiate the operation of a component that performs optical rule checking (ORC) operations on simulated silicon edges within the shared data.

26. The machine-readable medium of claim 20, wherein the sequences of instructions that cause the one or more electronic systems to import an integrated device layout into the hierarchical database comprises sequences of instructions that, when executed, cause the one or more electronic systems to analyze an original integrated device layout for redundant patterns and replacing one or more of the redundant patterns with cells that include redundant patterns.

27. The machine-readable medium of claim 20, wherein the sequences of instructions that cause the one or more electronic systems to import an integrated device layout to the hierarchical database comprises sequences of instructions that, when executed, cause the one or more electronic systems to convert one or more portions of the layout comprising a single layer to one or more portions of the layout comprising multi-level hierarchical layouts.

28. The machine-readable medium of claim 20, wherein the layout verification operations and the optical process correction (OPC) operations are performed on a set of edges the represent portions of the integrated device layout within the shared data.

29. The machine-readable medium of claim 20, wherein the integrated device layout comprises an integrated circuit (IC) layout.

30. An electronic data signal embodied in a data communications medium shared among a plurality of network devices comprising sequences of instructions that, when executed, cause one or more electronic systems to:

import an integrated device layout into a hierarchical database;

initiate the operation of one or more checking components that perform layout verification operations on the integrated device design; and

initiate the operation of a distinct software component that performs optical process correction (OPC) operations on the integrated device design.

31. The electronic data signal of claim 30, wherein the one or more checking components include a component that performs layout versus schematic (LVS) operations on the integrated device layout.

32. The electronic data signal of claim 30, wherein the one or more checking components include a component that performs design rule checking (DRC) operations on the integrated device layout.

33. The electronic data signal of claim 30, further comprising sequences of instructions that, when executed, cause the one or more electronic systems to initiate the operation of a component that performs phase shift mask (PSM) operations on the integrated device layout.

34. The electronic data signal of claim 30, further comprising sequences of instructions that, when executed, cause the one or more electronic systems to initiate the operation of a component that performs optical rule checking (ORC) operations on the integrated device layout.

35. The electronic data signal of claim 30, further comprising sequences of instructions that, when executed, cause the one or more electronic systems to initiate the operation of a component that performs optical rule checking (ORC) operations on simulated silicon edges.

36. The electronic data signal of claim 30, wherein the sequences of instructions that cause the one or more electronic systems to import an integrated device layout to the hierarchical database comprises sequences of instructions that, when executed, cause the one or more electronic systems to analyze an original integrated device design for redundant patterns and replace one or more of the redundant patterns with cells that include the redundant patterns.

37. The electronic data signal of claim 30, wherein the sequences of instructions that cause the one or more electronic systems to import an integrated device layout to the hierarchical database comprises sequences of instructions that, when executed, cause the one or more electronic systems to convert one or more portions of the layout comprising a single layer to one or more portions of the layout comprising multi-level hierarchical layouts.

38. The electronic data signal of claim 30, wherein the layout verification operations and the optical process correction (OPC) operations are performed on a set of edges the represent portions of the integrated device layout.

39. The electronic data signal of claim 30, wherein the integrated device design comprises an integrated circuit (IC) layout.

40. A machine readable medium on which is stored a sequence of programmed instructions to be executed by one or more processors in order to:

create a shared hierarchical database that represents components of an integrated circuit layout having a number of hierarchy layers, wherein redundant patterns of edges and/or polygons are described in the hierarchical database along with indication of where each such redundant pattern is found in the integrated circuit layout;

selectively promote edges or polygons in the database that interact to another layer of hierarchy such that each placement of the interacting edges or polygons can be separately analyzed; and

initiating a number of checking components and a distinct optical process correction component that analyze the data in the shared hierarchical database to ensure the manufacturability of the integrated circuit layout.