Semiconductor processing methods and semiconductor defect detection methods

• US 6,417,015 B2
• Filed: 05/29/2001
• Issued: 07/09/2002
• Est. Priority Date: 07/30/1998
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Mercaldi, Garry A., Nuttall, Michael
• Primary Examiner(s): Lebentritt, Michael S.
• Assistant Examiner(s): SMITH, BRADLEY
• Application Number:
  US09/870,157
• Publication Number:
  US 20010024836A1
• Time in Patent Office: 406 Days
• Field of Search: 438/14, 438/974, 438/928, 438/8, 438/687
• US Class Current: 438/14
• CPC Class Codes: H01L 22/24 Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change voltage contrast G01R31/311
• CPC Class Codes: Y10S 438/928 Front and rear surface processing
• CPC Class Codes: Y10S 438/974 Substrate surface preparation

Abstract

Semiconductor processing methods and defect detection methods are described. In one embodiment, a semiconductor wafer in process is provided and a material is formed or deposited over the wafer. The material is discernably deposited over defective wafer surface areas and not appreciably deposited over non-defective wafer surface areas. Subsequently, the wafer surface areas are inspected to identify defective areas. In another embodiment, a substrate is provided having an exposed region containing surface defects. A defect-highlighting material is substantially selectively deposited over surface defects and not appreciably over other exposed regions. The substrate is subsequently inspected for the deposited defect-highlighting material. In yet another embodiment, a dielectric layer is formed over a substrate outer surface and the substrate is processed in a manner which can give rise to a plurality of randomly-distributed dielectric layer features. A silicon-containing material is substantially selectively deposited and received over the randomly distributed dielectric layer features and not over other substrate areas. The substrate is subsequently inspected for the selectively-deposited silicon containing material.

Claims

1. A semiconductor defect detection method comprising:

providing a semiconductor wafer having an outer surface;

exposing the outer surface to conditions effective for depositing a polycrystalline material, the material being discernably deposited over defective areas and not appreciably deposited over non-defective areas; and

identifying defective areas.

2. The semiconductor defect detection method of claim 1, wherein the exposing comprises providing conditions effective for chemical vapor depositing a silicon-containing material.

3. The semiconductor defect detection method of claim 1, wherein the exposing comprises providing conditions effective for chemical vapor depositing polysilicon.

4. The semiconductor defect detection method of claim 1, wherein the exposing comprises providing a gaseous precursor of silicon to the outer surface at a temperature greater than or equal to about 650°

C., and at a pressure less than or equal to about 100 mTorr.

5. The semiconductor defect detection method of claim 1, wherein the exposing comprises providing a gaseous precursor of silicon to the outer surface at a temperature between about 650°

C. and 850°

C., and at a pressure between about 30 mTorr and 100 mTorr.

6. The semiconductor defect detection method of claim 1, wherein providing a semiconductor wafer having an outer surface comprises forming an oxide layer over at least a portion of the outer surface.

7. The semiconductor defect detection method of claim 1, wherein providing a semiconductor wafer having an outer surface comprises forming a gate oxide layer over at least a portion of the outer surface.

8. The semiconductor defect detection method of claim 1, wherein providing a semiconductor wafer having an outer surface comprises forming a gate oxide layer over at least a portion of the outer surface and the exposing comprises providing a gaseous precursor of silicon to the outer surface at a temperature between about 650°

C. and 850°

C., and at a pressure between about 30 mTorr and 100 mTorr.

9. A semiconductor defect detection method comprising:

providing a substrate having an essentially planar exposed region containing surface defects;

substantially selectively chemical vapor depositing a defect-highlighting material layer over the surface defects and not appreciably over other exposed regions; and

inspecting the substrate for the deposited defect-highlighting material.

10. The semiconductor defect detection method of claim 9, wherein the depositing of the defect-highlighting material comprises depositing a silicon-containing material.

11. The semiconductor defect detection method of claim 9, wherein the depositing of the defect-highlighting material comprises depositing polycrystalline silicon.

12. A semiconductor processing method comprising:

forming a dielectric layer over a substrate outer surface;

processing the substrate in a manner which can give rise to a plurality of randomly-distributed dielectric layer features;

exposing the substrate to conditions which provide discernable deposition of a silicon-containing material, essentially only over said randomly-distributed dielectric layer features; and

inspecting the substrate to identify discernable deposition of the silicon-containing material.

13. The semiconductor processing method of claim 12, wherein the forming comprises forming a gate dielectric layer.

14. The semiconductor processing method of claim 12, wherein the exposing of the substrate comprises:

providing the substrate within a chemical vapor deposition reactor; and

feeding a gaseous precursor of silicon into the reactor under conditions effective to deposit polysilicon, the conditions comprising a temperature greater than or equal to about 650°

C., and a pressure less than or equal to about 100 mTorr.

15. The semiconductor processing method of claim 12, wherein the exposing of the substrate comprises:

providing the substrate within a chemical vapor deposition reactor; and

feeding a gaseous precursor of silicon into the reactor under conditions effective to deposit polysilicon, the conditions comprising a temperature between about 650°

C. and 850°

C., and a pressure between about 30 mTorr and 100 mTorr.

16. A semiconductor processing method comprising:

forming a dielectric layer over a substrate outer surface, the dielectric layer having at least two discrete dielectric layer features which are desired to be identified; and

substantially selectively depositing a material over the dielectric layer, the substantially selective depositing highlighting the at least two discrete dielectric layer features.

17. The semiconductor processing method of claim 16, wherein the forming of the dielectric layer comprises forming a gate dielectric layer.

18. The semiconductor processing method of claim 17, wherein the depositing of the material over the substrate comprises depositing a silicon-containing material over the gate dielectric layer.

19. The semiconductor processing method of claim 16, wherein the depositing of the material over the substrate comprises:

providing the substrate within a chemical vapor deposition reactor; and

feeding a gaseous precursor of silicon into the reactor under conditions effective to deposit polysilicon, the conditions comprising a temperature greater than or equal to about 650°

C., and a pressure less than or equal to about 100 mTorr.

20. The semiconductor processing method of claim 16, wherein the depositing of the material over the substrate comprises depositing a polycrystalline silicon-containing material over the substrate.