Acoustic wave device face-down mounted on a substrate

• US 6,417,026 B2
• Filed: 01/05/2001
• Issued: 07/09/2002
• Est. Priority Date: 02/27/1998
• Status: Expired due to Fees

• Current Assignee: TDK Corporation
• Original Assignee: TDK Corporation
• Inventors: Kuwajima, Hajime, Gotoh, Masashi, Kanazawa, Jitsuo
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Chambliss, Alonzo
• Application Number:
  US09/754,327
• Publication Number:
  US 20010001293A1
• Time in Patent Office: 550 Days
• Field of Search: 438/106, 438/108, 438/109, 438/119, 438/124, 438/126, 438/127, 257/737, 257/738, 257/774, 257/780, 257/781, 257/786, 361/761, 361/764, 361/765, 228/180.22
• US Class Current: 438/108
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H03H 9/059 consisting of mounting pads or bumps
• CPC Class Codes: H03H 9/1085 the enclosure being defined by a non-uniform sealing mass covering the non-active sides of the BAW device
• CPC Class Codes: H03H 9/1092 the enclosure being defined by a cover cap mounted on an element forming part of the surface acoustic wave [SAW] device on the side of the IDT's

Abstract

In a chip device in which not only an electrode pattern 25 is provided on a main mounting surface 21a of a base 21 but also bump electrodes 22 are provided as external electrodes for face-down mounting, an electrically insulating layer 31 is provided to be put on at least a part of the main mounting surface 21a so as to remain edge portions which do not cover at least a part of the electrode pattern 25, and a protection layer 32 for protecting the main mounting surface is further provided at a distance from the main mounting surface 21a so as to be put on the electrically insulating layer 31, so that the bump electrodes 22 are connected to the electrode pattern 25 while being in contact with the edge portions of the electrically insulating layer 31 and the protection layer 32.

Claims

1. A method for producing a chip device comprising the steps of:

forming an electrode pattern and an active region on a main mounting surface of a device substrate;

forming at least one electrically insulating layer with on at least a part of said main mounting surface to form a frame body and to expose at least a part of said electrode pattern;

forming external electrodes after forming said frame body so that one end of each of said external electrodes is connected to said electrode pattern while said external electrodes are in contact with said edge portions of said electrically insulating layer; and

said insulating layer is interposed between said main mounting surface and a mount-side base substrate while not extending completely under said active region.

2. A method for producing a chip device according to claim 1, wherein said method further comprises a face-down mounting step of bonding said external electrodes to a mount-side substrate to thereby perform face-down mounting after the external electrode formation step, so that not only said external electrodes are connected to a conductor pattern of said mount-side substrate but also said electrically insulating layer is brought into close contact with both said main mounting surface and the surface of said mount-side substrate in said face-down mounting step.

3. A method for producing a chip according to claim 1, wherein said electrical insulating layer is formed on the main mounting surface before the electrode pattern is connected to the external electrode.

4. A method for producing a chip device comprising the steps of:

forming an electrode pattern and an active region on a main mounting surface of a device sustrate;

forming at least one electrically insulating layer on at least a part of said main mounting surface to form a frame body and to expose at least a part of said electrode pattern;

forming external electrodes after forming said at least one electrically insulating layer so that one end of each of said external electrodes is connected to said electrode pattern while said external electrodes are in contact with said edge portions of said electrically insulating layer,

said insulating layer is interposed between said main mounting surface and a mount-side base substrate while not extending completely under said active region.

5. A method for producing a chip device according to claim 4, wherein said method further comprises a face-down mounting step of bonding said external electrodes to said mount-side substrate to thereby perform face-down mounting after the external electrode formation step, so that not only said external electrodes are connected to a conductor pattern of said mount-side substrate but also said electrically insulating layer is brought into close contact with both said main mounting surface and the surface of said mount-side substrate in said face-down mounting step.

6. A method for producing a chip device according to claim 4, wherein said electrical insulating layer is formed on the main mounting surface before the electrode pattern is connected to the external electrode.