Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge
First Claim
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1. A method of forming a transistor with associated source and drain regions in the fabrication of an integrated circuit device comprising:
- providing a gate electrode overlying a gate dielectric layer on a substrate wherein a hard mask layer overlies a top surface of said gate dielectric layer;
forming an oxide layer overlying said substrate and sidewalls of said gate;
forming first spacers on sidewalls of said gate electrode and overlying said oxide layer;
forming source/drain extensions in said substrate using said first spacers as a mask;
forming second spacers on said first spacers;
forming source and drain regions in said substrate using said first and second spacers as a mask;
depositing a dielectric layer overlying said gate electrode and said oxide layer and planarizing said dielectric layer to said hard mask layer whereby said first spacers and said second spacers are exposed;
removing exposed said second spacers whereby said oxide layer underlying said second spacers is exposed;
removing exposed said oxide layer whereby said semiconductor substrate underlying said second spacers is exposed;
etching into exposed said semiconductor substrate to form a microtrench wherein said microtrench undercuts said gate oxide layer at an edge of said gate electrode;
filling said microtrench with an epitaxial oxide layer and planarizing said epitaxial oxide layer to said hard mask layer; and
thereafter patterning said dielectric layer to form third spacers on said epitaxial oxide layer to complete formation of said transistor and associated source and drain regions in said fabrication of said integrated circuit device.
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Abstract
A method for forming a transistor having low overlap capacitance by forming a microtrench at the gate edge to reduce effective dielectric constant is described. A gate electrode is provided overlying a gate dielectric layer on a substrate and having a hard mask layer thereover. An oxide layer is formed overlying the substrate. First spacers are formed on sidewalls of the gate electrode and overlying the oxide layer. Source/drain extensions are implanted. Second spacers are formed on the first spacers. Source/drain regions are implanted. A dielectric layer is deposited overlying the gate electrode and the oxide layer and planarized to the hard mask layer whereby the first and second spacers are exposed. The exposed second spacers and underlying oxide layer are removed. The exposed substrate underlying the second spacers is etched into to form a microtrench undercutting the gate oxide layer at an edge of the gate electrode. The microtrench is filled with an epitaxial oxide layer and planarized to the hard mask layer. The dielectric layer is patterned to form third spacers on the epitaxial oxide layer. The microtrench reduces the effective dielectric constant at the overlap between the gate and the source/drain extensions to complete formation of a transistor having low overlap capacitance.
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Citations
27 Claims
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1. A method of forming a transistor with associated source and drain regions in the fabrication of an integrated circuit device comprising:
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providing a gate electrode overlying a gate dielectric layer on a substrate wherein a hard mask layer overlies a top surface of said gate dielectric layer;
forming an oxide layer overlying said substrate and sidewalls of said gate;
forming first spacers on sidewalls of said gate electrode and overlying said oxide layer;
forming source/drain extensions in said substrate using said first spacers as a mask;
forming second spacers on said first spacers;
forming source and drain regions in said substrate using said first and second spacers as a mask;
depositing a dielectric layer overlying said gate electrode and said oxide layer and planarizing said dielectric layer to said hard mask layer whereby said first spacers and said second spacers are exposed;
removing exposed said second spacers whereby said oxide layer underlying said second spacers is exposed;
removing exposed said oxide layer whereby said semiconductor substrate underlying said second spacers is exposed;
etching into exposed said semiconductor substrate to form a microtrench wherein said microtrench undercuts said gate oxide layer at an edge of said gate electrode;
filling said microtrench with an epitaxial oxide layer and planarizing said epitaxial oxide layer to said hard mask layer; and
thereafter patterning said dielectric layer to form third spacers on said epitaxial oxide layer to complete formation of said transistor and associated source and drain regions in said fabrication of said integrated circuit device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of forming a transistor with associated source and drain regions in the fabrication of an integrated circuit device comprising:
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providing a gate electrode overlying a gate dielectric layer on a substrate wherein a hard mask layer overlies a top surface of said gate dielectric layer;
forming a first oxide layer overlying said substrate and sidewalls of said gate;
forming oxide spacers on sidewalls of said gate electrode and overlying said first oxide layer;
forming source/drain extensions in said substrate using said oxide spacers as a mask;
forming nitride spacers on said oxide spacers;
forming source and drain regions in said substrate using said oxide and said nitride spacers as a mask;
depositing a second oxide layer overlying said gate electrode and said first oxide layer and planarizing said second oxide layer to said hard mask layer whereby said oxide spacers and said nitride spacers are exposed;
removing exposed said nitride spacers whereby said first oxide layer underlying said nitride spacers is exposed;
removing exposed said first oxide layer whereby said substrate underlying said nitride spacers is exposed;
etching into exposed said substrate to form a microtrench wherein said microtrench undercuts said gate oxide layer at an edge of said gate electrode;
filling said microtrench with an epitaxial oxide layer and planarizing said epitaxial oxide layer to said hard mask layer; and
thereafter patterning said second oxide layer to form third spacers on said epitaxial oxide layer to complete formation of said transistor and associated source and drain regions in said fabrication of said integrated circuit device. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A method of forming a transistor with associated source and drain regions in the fabrication of an integrated circuit device comprising:
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providing a gate electrode overlying a gate dielectric layer on a substrate wherein a hard mask layer overlies a top surface of said gate dielectric layer;
re-oxidizing said substrate and said gate to form a first oxide layer overlying said substrate and sidewalls of said gate;
forming oxide spacers on sidewalls of said gate electrode and overlying said first oxide layer;
forming source/drain extensions in said substrate using said oxide spacers as a mask;
forming nitride spacers on said oxide spacers;
forming source and drain regions in said substrate using said oxide and said nitride spacers as a mask;
depositing a second oxide layer overlying said gate electrode and said first oxide layer and planarizing said second oxide layer to said hard mask layer whereby said oxide spacers and said nitride spacers are exposed;
removing exposed said nitride spacers whereby said first oxide layer underlying said nitride spacers is exposed;
removing exposed said first oxide layer whereby said substrate underlying said nitride spacers is exposed;
etching into exposed said substrate to form a microtrench wherein said microtrench undercuts said gate oxide layer at an edge of said gate electrode;
immersing said substrate in a hydrofluorosilicic acid solution supersaturated with silicic acid at room temperature whereby said microtrench is filled with an epitaxial oxide layer and planarizing said epitaxial oxide layer to said hard mask layer; and
thereafter patterning said second oxide layer to form third spacers on said epitaxial oxide layer to complete formation of said transistor and associated source and drain regions in said fabrication of said integrated circuit device. - View Dependent Claims (23, 24, 25, 26, 27)
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Current AssigneeChartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
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Original AssigneeChartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
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InventorsChan, Lap, Pan, Yang, Quek, Elgin, Lee, James Yong Meng, Pradeep, Yelehanka Ramachandramurthy, Zheng, Jia Zhen, Leung, Ying Keung, Sundaresan, Ravi
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Primary Examiner(s)Jackson, Jr., Jerome
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Assistant Examiner(s)Rao, Shrinivas H.
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Application NumberUS09/981,439Time in Patent Office264 DaysField of Search438/305, 438/229, 438/230, 438/303, 438/287, 438/785US Class Current438/303CPC Class CodesH01L 29/0649 Dielectric regions, e.g. Si...H01L 29/665 using self aligned silicida...H01L 29/66545 using a dummy, i.e. replace...H01L 29/66636 with source or drain recess...H01L 29/7834 with a non-planar structure...
