Method of manufacturing a structure for reducing leakage currents by providing isolation between adjacent regions of an integrated circuit
First Claim
1. A method of providing isolation between adjacent regions of an integrated circuit comprising the steps of:
- selecting a circuit layout for fabrication of said integrated circuit on a substrate, including defining adjacent substrate locations for a first region and a second region for which leakage current from said second region to said substrate is undesired during operation of said integrated circuit, at least said second region being an active region within which a dopant is to be introduced;
forming a guard layer over said substrate such that said guard layer resides over a peripheral portion of said second region, said peripheral portion of said second region extending along an edge of said first region; and
introducing said dopant into said second region to establish predetermined electrical characteristics within said second region, said guard layer inhibiting introduction of said dopant into said peripheral portion, thereby leaving a substantially dopant-free transition strip within said second region and along said edge of said first region to provide isolation between said second region and said first region.
8 Assignments
0 Petitions
Accused Products
Abstract
A fabrication method for providing isolation between adjacent regions of an integrated circuit includes providing a guard layer over field edges that are the interfaces between field oxide regions and diffusion regions in which dopant is introduced. The guard layer will inhibit introduction of dopant along the field-edge, so that a substantially dopant-free transition strip is formed. The transition strip inhibits current leakage from the active region to the field oxide region. In one embodiment, the active region is an active area diode, such as used to form an Active Pixel Sensor (APS) pixel. The guard layer is biased so as to further inhibit current leakage during circuit operation. In another embodiment, the method is used in the fabrication of transistors for APS pixels having an overlay photodiode structure.
-
Citations
13 Claims
-
1. A method of providing isolation between adjacent regions of an integrated circuit comprising the steps of:
-
selecting a circuit layout for fabrication of said integrated circuit on a substrate, including defining adjacent substrate locations for a first region and a second region for which leakage current from said second region to said substrate is undesired during operation of said integrated circuit, at least said second region being an active region within which a dopant is to be introduced;
forming a guard layer over said substrate such that said guard layer resides over a peripheral portion of said second region, said peripheral portion of said second region extending along an edge of said first region; and
introducing said dopant into said second region to establish predetermined electrical characteristics within said second region, said guard layer inhibiting introduction of said dopant into said peripheral portion, thereby leaving a substantially dopant-free transition strip within said second region and along said edge of said first region to provide isolation between said second region and said first region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A method of providing isolation between adjacent regions of an integrated circuit comprising the steps of:
-
selecting a circuit layout for fabrication of said integrated circuit on a substrate, including defining adjacent substrate locations for a first region and a second region for which leakage current from said second region to said substrate is undesired during operation of said integrated circuit, at least said second region being an active region within which a dopant is to be introduced;
forming a guard layer on said substrate such that said guard layer resides on a peripheral portion of said second region, said peripheral portion of said second region extending along an edge of said first region, said step of forming including patterning conductive material to define a gate of a MOSFET and to provide said guard layer along an interface between a source/drain region of said MOSFET and a field oxide region, said transition strip thereby isolating said source/drain region from said field oxide region; and
introducing said dopant into said second region to establish predetermined electrical characteristics within said second region, said guard layer inhibiting introduction of said dopant into said peripheral portion, thereby leaving a transition strip within said second region and along said edge of said first region. - View Dependent Claims (13)
-
Specification