Method of forming solder bumps with reduced undercutting of under bump metallurgy (UBM)

• US 6,417,089 B1
• Filed: 08/04/2000
• Issued: 07/09/2002
• Est. Priority Date: 01/03/2000
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Chang Hun, Kim, Byung Soo
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): FOONG, SUK SAN
• Application Number:
  US09/632,903
• Time in Patent Office: 704 Days
• Field of Search: 438/612, 438/FOR.343, 438/FOR.369
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

In a method of forming solder bumps, each solder bump is formed over a corresponding one of a plurality of chip pads of an active upper surface of a semiconductor device. An under bump metallurgy (UBM) is formed on the upper surface of the semiconductor device and the chip pads. A photoresist layer is deposited thereto and patterned to expose the under bump metallurgy on the chip pads. The solder bumps are formed on the under bump metallurgy exposed from the photoresist patterns, and the photoresist patterns are removed. An intermetallic compound layer (IMC) is formed on an interface between the solder bump and the under bump metallurgy by heating the solder bump at a temperature lower than a melting point of the solder bump. Then, the under bump metallurgy is etched by using the IMC as a mask, and the solder bumps are reflowed. The present invention obtains sufficient joint area between the under bump metallurgy and the solder bump as well as joint area between the under bump metallurgy and the buffer layer, and reduces the undercutting of the under bump metallurgy and thereby improves the mechanical and the electrical reliability of the solder bumps.

Claims

1. A method of forming solder bumps on an active upper surface of a semiconductor device including a plurality of chip pads, said method comprising:

forming an under bump metallurgy (UBM) on a surface of the semiconductor device including the chip pads;

forming photoresist patterns on said under bump metallurgy, said photoresist patterns exposing the under bump metallurgy;

forming said solder bumps directly on a pure metal layer of said under bump metallurgy exposed from said photoresist patterns;

removing said photoresist patterns;

forming an intermetallic compound layer on an interface between said solder bumps and said under bump metallurgy by first heating said solder bumps at a first temperature lower than a melting point of the solder bumps;

etching said under bump metallurgy using said intermetallic compound layer as a mask; and

reflowing said solder bumps by second heating said solder bumps at a second temperature higher than the first temperature.

2. The method of claim 1, wherein an insulation layer is formed on the upper surface of the semiconductor device, said insulation layer having openings for exposing the chip pads, and wherein said forming the under bump metallurgy comprises forming said under bump metallurgy on said insulation layer and the chip pads.

3. The method of claim 2, wherein said insulation layer comprises a passivation layer and a buffer layer, said passivation layer comprising an oxide layer or a nitride layer and said buffer layer being made of a polymer selected from the group consisting of polyimide, benzocyclobutene(BCB), polybenzoxazole(PBO), and epoxy.

4. The method of claim 1, wherein said forming the under bump metallurgy comprises forming a first metal layer on the upper surface of the semiconductor device including the chip pads, and forming a second metal layer on said first metal layer;

and

wherein said first and said second metal layers are respectively comprised of a metal selected from the group consisting of chromium(Cr), copper(Cu), nickel(Ni), titanium(Ti), tungsten(W), vanadium(V), palladium(Pd), aluminum(Al), gold(Au), and their alloys.

5. The method of claim 1, wherein said forming the under bump metallurgy comprises forming a nickel layer on the upper surface of the semiconductor device including the chip pads, and forming a copper layer on said nickel layer.

6. The method of claim 5, wherein said forming the intermetallic compound layer comprises forming a copper-tin(Cu—

Sn) intermetallic compound layer on the interface between said solder bumps and said copper layer.

7. The method of claim 1, wherein said forming the solder bumps comprises electroplating solder on the under bump metallurgy exposed from the photoresist patterns.

8. The method of claim 1, wherein the solder bumps have a melting point of approximately 320°

C., and wherein the intermetallic compound layer is formed by first heating the solder bumps at approximately 300°

C.

9. The method of claim 1, wherein the solder bumps have a melting point of approximately 183°

C., and wherein the intermetallic compound layer is formed by first heating the solder bumps to approximately 170°

C.

10. The method of claim 1, wherein, for each solder bump, the perimeter of the intermetallic compound layer extends beyond the diameter of the solder bumps following the first heating and prior to reflow of the solder bumps by the second heating.

11. The method of claim 1 wherein the solder bumps are formed over the chip pads.