Process for producing metal interconnections and product produced thereby

• US 6,417,572 B1
• Filed: 07/16/1999
• Issued: 07/09/2002
• Est. Priority Date: 08/13/1997
• Status: Expired due to Term

• Current Assignee: X Corp. (f/k/a Twitter, Inc.) (X Holdings Corp.)
• Original Assignee: International Business Machines Corporation
• Inventors: Sullivan, Timothy D., Chidambarrao, Dureseti, Shaw, Thomas M., Filippi, Ronald G., Wachnik, Richard A., Rosenberg, Robert
• Primary Examiner(s): Cao, Phat X.
• Application Number:
  US09/354,592
• Time in Patent Office: 1,089 Days
• Field of Search: 257/773, 257/775, 257/734, 257/774, 257/764, 257/765
• US Class Current: 257/773
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A process for producing a multi-level semiconductor device having metal interconnections with insulating passivation layers and the product produced thereby. The product and process improve the resistance of the metallization interconnections to extrusion-short electromigration failures by preventing the insulating passivation layers from cracking. The product and process also reduce the level of resistance saturation or the maximum resistance shift caused by electromigration. By replacing wide-line metallization interconnection conducting lines surrounded by insulating passivation layers with two or more narrow, parallel conducting lines having aspect ratios less than or equal to unity with passivation layers located in between, the incidence of passivation cracking and extrusion-short failures is reduced. The process is especially suited for use in multi-level wiring structures in which the wiring levels have diffusion barriers between the wiring levels caused by redundant metallization layers, interlevel connections, or both.

Claims

1. An integrated circuit comprising:

a semiconductor substrate and a wide-line interconnect on said substrate, said wide-line interconnect including a plurality of narrow interconnects to minimize electromigration, said plurality of narrow interconnects extending, and separated from each other for a portion of a length that lies between a cathode or electron current source and an anode or electron current sink, said plurality of narrow interconnects lies closer to said anode or electron current sink of said wide-line interconnect, each narrow interconnect having a width, W, and a height, H, such that each narrow interconnect has an aspect ratio defined as W/H which is less than or equal to unity, and said plurality of narrow interconnects being multiple layers of thin film metallization layers.

2. The integrated circuit of claim 1, wherein said aspect ratio is below about 0.67.

3. The integrated circuit of claim 1, wherein said plurality of narrow interconnects are connected by interlevel connection studs.

4. The integrated circuit as recited in claim 3, wherein said interlevel connection studs are made of tungsten.

5. The integrated circuit as recited in claim 1, wherein said plurality of narrow interconnects are separated from each other by an insulating passivation layer.

6. The integrated circuit of claim 5, wherein said insulating passivation layer comprises a material selected from the group consisting of silicon dioxide, polyimide, parylene, Dow Cyclotene, Dow SiLK, diamond like carbon, silicon nitride, polytetraflouro-ethylene, and a nano-pore containing material.

7. The integrated circuit as recited in claim 1, wherein one or more of said plurality of narrow interconnects each comprise a multi-layered metallization structure comprising a conductive metallization layer and at least one redundant metallization layer disposed on said conductive metallization layer.

8. The integrated circuit of claim 7, wherein said conductive metallization layer comprises a material selected from the group consisting of gold, copper, copper alloys, aluminum, and an aluminum-copper alloy, and said at least one redundant metallization layer comprises a material selected from the group consisting of titanium, tantalum, tungsten, titanium-tungsten alloy, titanium aluminide, titanium nitride, and tantalum nitride.

9. The integrated circuit as recited in claim 8, wherein said aluminum-copper alloy comprises 0.5 wt % copper.

10. An integrated circuit as recited in claim 1, wherein said plurality of narrow interconnects are parallel lines disposed between a cathode or electron current source and an anode or electron current sink such that the parallel lines are disposed closer to an anode or electron current sink.

11. The integrated circuit as recited in claim 1, wherein said plurality of narrow interconnects are parallel lines disposed between said cathode or electron current source and said anode or electron current sink, such that the parallel lines are disposed closer to said anode or electron current sink, with said parallel lines being joined together at multiple locations along their length between said cathode or electron current source and said anode or electron current sink, said parallel lines joined closer to said anode or electron current sink and being separated from each other along the length of said wide-line interconnect and along a width of said wide-line interconnect.

12. The integrated circuit as recited in claim 1, wherein said interconnects are constrained from diffusing by diffusion blocking material on all surfaces thereof.

13. An electrically conductive stripe comprising:

a plurality of narrow electrically conductive stripes separated from each other and extending for a portion of a length that lies between a cathode or electron current source and an anode or electron current sink, said plurality of narrow electrically conductive stripes lies closer to said anode or electron current sink of said electrically conductive stripe, each narrow electrically conductive stripe having a width, W, and a height, H, wherein said narrow electrically conductive stripe has an aspect ratio defined as W/H which is less than 0.5, and said plurality of narrow electrically conductive stripes being multiple layers of thin film metallization layers.

14. The electrically conductive stripe as recited in claim 13, wherein each narrow electrically conductive stripe has a multi-layered metallization structure comprising a conductive metallization layer and at least one redundant metallization layer disposed on said conductive metallization layer.

15. The electrically conductive stripe as recited in claim 14, wherein said conductive metallization layer comprises a material selected form the group consisting of gold, copper, copper alloys, aluminum, and an aluminum-copper alloy, and said at least one redundant metallization layer comprises a material selected from the group consisting of titanium, tantalum, tungsten, titanium-tungsten alloy, titanium aluninide, titanium nitride, and tantalum nitride.

16. The electrically conductive stripe as recited in claim 15, wherein said aluminum-copper alloy comprises 0.5 wt % copper.

17. An integrated circuit comprising:

a semiconductor substrate and a plurality of narrow interconnects formed thereon designed to minmize electromigration, said plurality of narrow interconnects lie between a cathode or electron current source and an anode or electron current sink, said plurality of narrow interconnects lies closer to said anode or electron current sink, said plurality of interconnects being electrically connected and having a width, W, and a height, H, such that the interconnects have an aspect ratio defined as W/H which is less than or equal to unity, said plurality of interconnects include a plurality of insulating passivation layers disposed alternately between said plurality of said interconnects, said plurality of insulating passivation layers being of a high modulus material, and insulating passivation layers above said plurality of insulating passivation layers being of a low dielectric constant interlevel dielectric.

18. The integrated circuit of claim 17, wherein said high modulus material is selected from the group consisting of silicon dioxide, silicon nitride, and diamond like carbon.

19. The integrated circuit of claim 17, wherein said low dielectric constant interlevel dielectric is polyimide.

20. An integrated circuit comprising:

a semiconductor substrate and an interconnect formed thereon, said interconnect having along a length thereof a first region of width W1 and a second region of width W2, wherein W1>

W2 and said first and second regions are electrically connected, said interconnect along said length lies between a cathode or electron current source and an anode or electron current sink, with said interconnect along said length being closer to said anode or electron current sink;

said interconnect has a plurality of said first regions and a plurality of said second regions that lie between said cathode or electron current source and said anode or electron current sink, said plurality of said first regions and said plurality of said second regions lie closer to said anode or electron current sink, and said first and second regions alternate along the length of said interconnect;

said first regions of said interconnect each includes a plurality of narrow interconnects to minimize electromigration, said plurality of narrow interconnects lie between said cathode or electron current source and said anode or electron current sink, said plurality of narrow interconnects lies closer to said anode or electron current sink, said plurality of narrow interconnects separated form each other along a length of each said first region, and said plurality of narrow interconnects being electrically connected to said interconnect;

said interconnect has a width W, and a height H, and each narrow interconnect in each of said first regions has an aspect ratio of W/H which is less than or equal to unity.

21. The integrated circuit of claim 20, wherein said plurality of narrow interconnects are of multiple layers of thin film metallization, and said plurality of narrow interconnects having sides with diffusion blocking material to constrain diffusion.