Process for producing metal interconnections and product produced thereby
First Claim
1. An integrated circuit comprising:
- a semiconductor substrate and a wide-line interconnect on said substrate, said wide-line interconnect including a plurality of narrow interconnects to minimize electromigration, said plurality of narrow interconnects extending, and separated from each other for a portion of a length that lies between a cathode or electron current source and an anode or electron current sink, said plurality of narrow interconnects lies closer to said anode or electron current sink of said wide-line interconnect, each narrow interconnect having a width, W, and a height, H, such that each narrow interconnect has an aspect ratio defined as W/H which is less than or equal to unity, and said plurality of narrow interconnects being multiple layers of thin film metallization layers.
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Accused Products
Abstract
A process for producing a multi-level semiconductor device having metal interconnections with insulating passivation layers and the product produced thereby. The product and process improve the resistance of the metallization interconnections to extrusion-short electromigration failures by preventing the insulating passivation layers from cracking. The product and process also reduce the level of resistance saturation or the maximum resistance shift caused by electromigration. By replacing wide-line metallization interconnection conducting lines surrounded by insulating passivation layers with two or more narrow, parallel conducting lines having aspect ratios less than or equal to unity with passivation layers located in between, the incidence of passivation cracking and extrusion-short failures is reduced. The process is especially suited for use in multi-level wiring structures in which the wiring levels have diffusion barriers between the wiring levels caused by redundant metallization layers, interlevel connections, or both.
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Citations
21 Claims
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1. An integrated circuit comprising:
a semiconductor substrate and a wide-line interconnect on said substrate, said wide-line interconnect including a plurality of narrow interconnects to minimize electromigration, said plurality of narrow interconnects extending, and separated from each other for a portion of a length that lies between a cathode or electron current source and an anode or electron current sink, said plurality of narrow interconnects lies closer to said anode or electron current sink of said wide-line interconnect, each narrow interconnect having a width, W, and a height, H, such that each narrow interconnect has an aspect ratio defined as W/H which is less than or equal to unity, and said plurality of narrow interconnects being multiple layers of thin film metallization layers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An electrically conductive stripe comprising:
a plurality of narrow electrically conductive stripes separated from each other and extending for a portion of a length that lies between a cathode or electron current source and an anode or electron current sink, said plurality of narrow electrically conductive stripes lies closer to said anode or electron current sink of said electrically conductive stripe, each narrow electrically conductive stripe having a width, W, and a height, H, wherein said narrow electrically conductive stripe has an aspect ratio defined as W/H which is less than 0.5, and said plurality of narrow electrically conductive stripes being multiple layers of thin film metallization layers. - View Dependent Claims (14, 15, 16)
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17. An integrated circuit comprising:
a semiconductor substrate and a plurality of narrow interconnects formed thereon designed to minmize electromigration, said plurality of narrow interconnects lie between a cathode or electron current source and an anode or electron current sink, said plurality of narrow interconnects lies closer to said anode or electron current sink, said plurality of interconnects being electrically connected and having a width, W, and a height, H, such that the interconnects have an aspect ratio defined as W/H which is less than or equal to unity, said plurality of interconnects include a plurality of insulating passivation layers disposed alternately between said plurality of said interconnects, said plurality of insulating passivation layers being of a high modulus material, and insulating passivation layers above said plurality of insulating passivation layers being of a low dielectric constant interlevel dielectric. - View Dependent Claims (18, 19)
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20. An integrated circuit comprising:
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a semiconductor substrate and an interconnect formed thereon, said interconnect having along a length thereof a first region of width W1 and a second region of width W2, wherein W1>
W2 and said first and second regions are electrically connected, said interconnect along said length lies between a cathode or electron current source and an anode or electron current sink, with said interconnect along said length being closer to said anode or electron current sink;
said interconnect has a plurality of said first regions and a plurality of said second regions that lie between said cathode or electron current source and said anode or electron current sink, said plurality of said first regions and said plurality of said second regions lie closer to said anode or electron current sink, and said first and second regions alternate along the length of said interconnect;
said first regions of said interconnect each includes a plurality of narrow interconnects to minimize electromigration, said plurality of narrow interconnects lie between said cathode or electron current source and said anode or electron current sink, said plurality of narrow interconnects lies closer to said anode or electron current sink, said plurality of narrow interconnects separated form each other along a length of each said first region, and said plurality of narrow interconnects being electrically connected to said interconnect;
said interconnect has a width W, and a height H, and each narrow interconnect in each of said first regions has an aspect ratio of W/H which is less than or equal to unity. - View Dependent Claims (21)
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Specification