DC-to-DC converter

• US 6,417,653 B1
• Filed: 04/30/1997
• Issued: 07/09/2002
• Est. Priority Date: 04/30/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Massie, Harold L., Wickersham, Robert D., Payton, Edward L.
• Primary Examiner(s): Vu, Bao Q.
• Application Number:
  US08/848,842
• Publication Number:
  US 20020039017A1
• Time in Patent Office: 1,896 Days
• Field of Search: 323/282, 323/285, 323/284, 323/286
• US Class Current: 323/282
• CPC Class Codes: H02M 1/0022 the disturbance parameters being input voltage fluctuations
• CPC Class Codes: H02M 1/0025 Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
• CPC Class Codes: H02M 1/088 for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/04206 in field-effect transistor switches
• CPC Class Codes: H03K 17/165 by feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Briefly, in accordance with one embodiment of the invention, a DC-to-DC converter includes: a circuit configuration to modify the set point of the output voltage signal level of the DC-to-DC converter circuit in response to a transient signal by an amount related, at least in part, to the magnitude of the transient signal. Briefly, in accordance with yet another embodiment of the invention, a DC-to-DC converter circuit includes: a high-side and a low-side voltage switching device. The switching devices are coupled in a circuit configuration to apply a control voltage signal to each switching device based, at least in part, on the state of the other switching device.

Claims

1. A DC-to-DC converter circuit comprising:

a circuit configuration to modify the set point of the output voltage signal of the DC-to-DC converter circuit in response to a transient signal by an amount related, at least in part, to the magnitude of the transient signal.

2. The DC-to-DC converter circuit of claim 1, and further comprising, as part of the circuit configuration, a portion to maintain the set point at a voltage signal level above a nominal voltage signal level midway between a first and a second voltage signal level during substantially no output loading conditions.

3. The DC-to-DC converter circuit of claim 1, wherein the circuit configuration is adapted to modify the set point by sampling a voltage signal related to the output current signal and adjusting a set point reference voltage signal based, at least in part, on said voltage signal related to the output current signal.

4. The DC-to-DC converter circuit of claim 3, wherein the sampled voltage signal comprises a negative voltage signal.

5. The DC-to-DC converter circuit of claim 1, wherein said DC-to-DC converter circuit comprises a synchronous rectifier circuit.

6. The DC-to-DC converter circuit of claim 1, wherein said DC-to-DC converter circuit is embodied on an integrated circuit chip.

7. The DC-to-DC converter circuit of claim 1, wherein said transient signal comprises one of a transient voltage signal and a transient current signal.

8. A DC-to-DC converter comprising:

a high-side and a low-side switching device, the switching devices being coupled in a circuit configuration to prevent cross-conduction by applying a control voltage to each switching device based, at least in part, on the state of the other switching device;

wherein the circuit configuration is adapted to clamp the control voltage of each of said switching devices in a low state while a control voltage of the other switching device is in a high state.

9. The DC-to-DC converter circuit of claim 8, wherein at least one of said switching devices comprises a transistor.

10. The DC-to-DC converter circuit of claim 8, wherein said converter circuit comprises a synchronous rectifier circuit.

11. The DC-to-DC converter circuit of claim 8, wherein the circuit configuration is coupled so that the control voltage of the other switching device is also applied as the control voltage of another switching device so as to clamp said control voltage signal of each of said switching devices to ground while a control voltage of the other switching device is in a high state.

12. A method of modifying the set point of the output voltage signal of a DC-to-DC converter circuit comprising:

sampling a voltage signal related to the output current signal; and

adjusting the set point based, at least in part, on the magnitude of the sampled voltage signal.

13. The method of claim 12, wherein sampling a voltage signal related to the output current signal comprises sampling a negative voltage signal.

14. The method of claim 13, wherein adjusting the set point based, at least in part, on the magnitude of the sampled voltage signal comprises adjusting a set point reference voltage signal.

15. The method of claim 14, wherein adjusting a set point reference voltage signal comprises summing the set point reference voltage signal with the negative voltage signal.

16. A method of preventing cross-conduction in the output stage of a DC-to-DC converter circuit including a synchronous rectifier circuit comprising:

applying a control voltage signal to each of a high-side and a low-side switching device based at least in part, on the state of the other switching device;

wherein said applying a control voltage signal includes clamping the control voltage signal of each of the high-side and the low-side switching devices in a low state while the other switching device is in a high state.

17. The method of claim 16, wherein said high-side switching device comprises a transistor and said low-side switching device comprises a transistor.

18. The method of claim 17, wherein the high-side transistor comprises a field-effect transistor (FET) and the low-side transistor comprises an FET.

19. The method of claim 16, wherein clamping the control voltage signal of each of the high-side and the low-side switching devices in a low state comprises clamping the control signal to ground.