Noise reduction circuits

• US 6,417,707 B1
• Filed: 02/03/2000
• Issued: 07/09/2002
• Est. Priority Date: 07/07/1997
• Status: Expired due to Fees

• Current Assignee: Toric Limited
• Original Assignee: Toric Limited
• Inventors: Downie, Neil Alexander, Underhill, Michael James
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US09/446,648
• Time in Patent Office: 887 Days
• Field of Search: 327/34, 327/551, 327/311, 327/165, 327/552, 327/122, 327/336
• US Class Current: 327/165
• CPC Class Codes: H03K 5/003 Changing the DC level reinsertion of dc component of a television signal H04N5/16
• CPC Class Codes: H03K 5/082 with an adaptive threshold
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle
• CPC Class Codes: H03K 5/19 Monitoring patterns of pulse trains indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02

Abstract

A noise reduction circuit useful as a clock restoration circuit includes a DC removal circuit for removing a DC level from an input pulse train, an integrator for integrating the input pulse train after a DC level has been removed, a comparator for comparing the integrator output with a threshold value (V_mp) to detect for a missing pulse, a pulse generator inserting into the input pulse train an additional pulse delayed with respect to any missing pulse, and an output circuit for generating an output pulse train from the integrator output.

Claims

1. A clock restoration circuit for reducing noise in an input pulse train consisting of pulses having a nominal periodicity and from which one or more pulses is missing, the clock restoration circuit including,

DC removal means for removing a DC level from the input pulse train,

integrator means for integrating the input pulse train after said DC level has been removed therefrom by the DC removal means,

detection means for receiving an output from the integrator means and for detecting from said output a missing pulse in the input pulse train,

pulse generating means responsive to the detection means for inserting into the input pulse train an additional pulse delayed with respect to said missing pulse detected by the detection means and

output means for generating an output pulse train from said output from the integrator means.

2. A circuit as claimed in claim 1, wherein said output means is effective to reduce phase noise caused by a delay of said additional pulse.

3. A circuit as claimed in claim 2, wherein said output means comprises a comparator for comparing the output from the integrator means with a reference level and for generating a comparison signal as a result of the comparison and an output monostable circuit for deriving the output pulse train from the comparison signal.

4. A circuit as claimed in claim 1 including input means for deriving said input pulse train from a waveform received from an external source.

5. A circuit as claimed in claim 4, wherein said input means is an input monostable circuit.

6. A circuit as claimed in claim 1, comprising frequency-doubling means for deriving said input pulse train from a waveform received from an external source and wherein said output means includes a divide-by-two circuit.

7. A circuit as claimed in claim 1 wherein said detection means comprises a comparator for comparing the output from said integrator means with a threshold value which is preset so as to exceed the highest attainable value of the output from the integrator means when no pulse is missing, and said pulse generating means is arranged to insert said additional pulse into the input pulse train when said comparator detects that the output from the integrator means has crossed said threshold value.

8. A circuit as claimed in claim 7, wherein said pulse generating means comprises a monostable circuit triggered by a detection signal output by said comparator when the value of the output from the integrator means has crossed said threshold value.

9. A circuit as claimed in claim 8, wherein said input pulse train is supplied to the integrator means via an OR gate, said monostable circuit of the pulse generating means being connected to a first input of the OR gate and said input pulse train being supplied to a second input of the OR gate.

10. A circuit as claimed in claim 1 including control means responsive to an output from said detection means for disabling the DC removal means upon detection by the detection means of said missing pulse and for re-enabling the DC removal means upon detection by the detection means of the next pulse in the input pulse train.

11. A circuit as claimed in claim 1 including circuit means for reducing phase jitter in said output pulse train.

12. A circuit as claimed in claim 11 wherein said circuit means comprises further DC removal means for removing a DC level from the output pulse train, further integrator means for integrating the output pulse train after said DC level has been removed therefrom to produce an integrated output and processning means for deriving from the integrated output said output pulse train having reduced phase jitter.

13. A circuit as claimed in claim 12 wherein said processing means comprises a comparison circuit for comparing the integrated output from the further integrator means with a reference level and for generating a comparison signal as a result of the comparison, and an output circuit for extracting from the comparison signal said output pulse train having reduced phase jitter.

14. A circuit as claimed in claim 13, wherein said output circuit is a monostable circuit.

15. A circuit as claimed in claim 6, wherein said frequency doubling means comprises means for deriving a first pulse train from a received waveform, said first pulse train consisting of pulses triggered by positive-going transitions, means for deriving a second pulse train from the received waveform, said second pulse train consisting of pulses triggered by negative-going transitions and means for combining the first and second pulse trains to form said input pulse train.

16. A circuit as claimed in claim 1 including a monostable circuit for causing pulses of the input pulse train to have the same pulse width.

17. A phase noise reduction circuit for reducing phase noise in an input pulse train consisting of pulses having a nominal frequency f, the phase noise reduction circuit comprising,

means for deriving a first pulse train from the input pulse train, the first pulse train consisting of pulses triggered by positive-going transitions of the pulses forming the input pulse train,

means for deriving a second pulse train from the input pulse train, the second pulse train consisting of pulses triggered by negative-going transitions of the pulses forming the input pulse train,

combining means for combining the first and second pulse trains to form a combined pulse train,

DC removal means for removing a DC level from the combined pulse train,

integrator means for integrating the combined pulse train after said DC level has been removed from the combined pulse train by the DC removal means to produce an integrated output and

processing means for deriving from the integrated output an output pulse train at said nominal frequency f.

18. A circuit as claimed in claim 17 wherein said processing means comprises a comparator for comparing the integrated output with a reference level and for generating a comparison signal as a result of the comparison, and an output circuit for extracting said output pulse train from the comparison signal.

19. A circuit as claimed in claim 18 wherein said output circuit is a divide-by-two circuit.

20. A clock restoration circuit for reducing noise in an input pulse train consisting of pulses which have a nominal periodicity and amongst which one or more spurious additional pulse is present, the clock restoration circuit including,

DC removal means for removing a DC level from the input pulse train,

integrator means for integrating the input pulse train after said DC level has been removed from the input pulse train by the DC removal means,

pulse deletion means for deleting a said spurious additional pulse from the input pulse train, said pulse deletion means comprising pulse generating means for receiving an output from said integrator means and for generating blanking pulses in response to said output and means for combining said blanking pulses with said pulses of said input pulse train to delete said one or more spurious additional pulse and

output means for deriving an output pulse train from said output from the integrator means.

21. A circuit as claimed in claim 20 wherein the pulse generating means generates a blanking pulse after each said periodic pulse.

22. A circuit as claimed in claim 20 including means for detecting for a missing pulse in the input pulse train and means for inserting a pulse in the input pulse train in response to detection of a missing pulse.

23. A circuit as claimed in claim 20 including input means for deriving the input pulse train from a waveform received from an external source.

24. A circuit as claimed in claim 23 wherein the input means is an input monostable circuit.

25. A circuit as claimed in claim 20 including frequency doubling means for deriving said input pulse train from a received waveform and wherein said output means includes a divide-by-two circuit.

26. A circuit comprising two circuits each as claimed in claim 20 wherein one of said two circuits acts on an input waveform, another of said two circuits acts on the inverse of the input waveform, and each of whose outputs are fed to a divide-by-two circuit, the outputs of the divide-by-two circuits being combined in an OR gate to form a single common output.

27. A circuit comprising two circuits each as claimed in claim 20 wherein one of said two circuits acts on an input waveform, another of said two circuits acts on the inverse of the input waveform, and each of whose outputs are fed to the set and reset inputs of a flip-flop, the output of which forms a single common output.

28. A circuit as claimed in claim 25 wherein said frequency doubling means comprises means for deriving a first pulse train from a received waveform, the first pulse train being triggered by positive-going transitions, means for deriving a second pulse train from said received waveform, the second pulse train being triggered by negative-going transitions, and means for combining the first and second pulse trains to form the input pulse train.

29. A circuit as claimed in claim 20 wherein said output means comprises a monostable circuit.

30. A circuit as claimed in claim 20 wherein said output means includes means for reducing time jitter in the output pulse train.

31. A circuit as claimed in claim 20 wherein said means for combining comprises a latch circuit having a terminate input for receiving said blanking pulses.

32. A circuit as claimed in claim 20 including a monostable circuit for causing pulses of the input pulse train to have the same pulse width.

33. A circuit for reducing phase noise in an input pulse train consisting of pulses having a nominal periodicity, the circuit including DC removal means for removing a DC level from the input pulse train,

integrator means for integrating the input pulse train after said DC level has been removed from said input pulse train by the DC removal means and at least two detection means for producing different output pulse trains in response to an output from the integrator means and to respectively different reference signals whereby each said output pulse train contains periodic transitions having a respective phase relationship to transitions of the input pulse train dependent on the corresponding said reference signal.

34. A circuit as claimed in claim 33 including a plurality of said detection means and output means for deriving one or more substantially jitter-free output pulse trains from said output pulse trains respectively produced by one or more pairs of said detection means.

35. A circuit as claimed in claim 34 wherein said output means includes a latch circuit and toggling means for toggling the latch circuit between its output logic states in response to the output pulse trains produced by a said pair of detection means whereby to generate a corresponding said substantially jitter-free output pulse train.

36. A circuit as claimed in claim 35 wherein aid toggling means comprises a pair of monostable circuits each connected to receive the output pulse train produced by a different detection means of said pair of detection means.

37. A circuit as claimed in claim 33 including means for deleting a spurious additional pulse in the input pulse train.

38. A circuit as claimed in claim 33 including means for inserting a pulse into the input pulse train upon detection of a missing pulse in the input pulse train.

39. A circuit as claimed in claim 33 including a monostable circuit for causing pulses in the input pulse train to have the same pulse width.