Amplifier with bias compensation using a current mirror circuit

• US 6,417,735 B1
• Filed: 12/07/2001
• Issued: 07/09/2002
• Est. Priority Date: 12/07/2001
• Status: Expired due to Fees

• Current Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Luo, Sifen
• Primary Examiner(s): Lee, Benny
• Assistant Examiner(s): Choe, Henry
• Application Number:
  US10/020,076
• Time in Patent Office: 214 Days
• Field of Search: 330/288, 330/296, 330/302
• US Class Current: 330/296
• CPC Class Codes: H03F 1/302 in bipolar transistor amplifiers H03F1/303, H03F1/305, H03F1/307 take precedence
• CPC Class Codes: H03F 3/19 with semiconductor devices only

Abstract

A power amplifier circuit comprises an amplifying transistor and a dc bias circuit. The dc bias circuit comprises a first transistor in a current mirror with the amplifying transistor, and a second transistor to provide the base currents to both the amplifying transistor and the first transistor. A dc bias power source is coupled to the base of the second transistor through a resistor and an inductor connected in series. A bypass capacitor is coupled between a ground and a node between the resistor and the inductor. Thus, the reduced voltage drop across the base-emitter junction of the amplifying transistor due to an increased input power is compensated. Furthermore, by properly scaling the emitter area ratio between the amplifying transistor and the first transistor, and/or the ratio between a bias resistor and a corresponding resistor coupled with the mirroring first transistor, the quiescent current in the amplifying transistor can be made to be in direct proportion to that of the first transistor.

Claims

1. An amplifier circuit comprising:

an amplifying transistor;

a dc bias circuit comprising;

a first transistor forming a current mirror with said amplifying transistor with their bases coupled at a first common node and their emitters coupled to a common terminal;

a second transistor having an emitter coupled to said first common node and a base coupled to a collector of said first transistor at a second common node;

a bias power source coupled to said second common node through a resistor and an inductor connected in series at a third common node, and directly coupled to a collector of said second transistor as well;

wherein said dc bias circuit further comprises a bypass capacitor coupled between said third common node and a ground.

2. The power amplifier circuit of claim 1 wherein said capacitor is an off-chip capacitor.

3. The power amplifier circuit of claim 1 wherein said capacitor is an adjustable capacitor.

4. The power amplifier circuit of claim 1 wherein said dc bias circuit further comprises a bias resistor coupled between said base of said amplifying transistor and said first common node, and another resistor coupled between said base of said first transistor and said first common node.

5. The power amplifier of claim 4 wherein an emitter area ratio between said amplifying transistor and said first transistor and a resistance ratio between said bias resistor and said another resistor are configured such that a quiescent current in said amplifying transistor is directly proportional to that in said first transistor.

6. The power amplifier of claim 5 wherein said emitter area ratio of said amplifying transistor to said first transistor is 8 to 1.

7. The power amplifier of claim 1 wherein said common terminal is a common ground.

8. A power amplifier circuit, comprising:

an amplifying transistor;

a dc bias circuit having a first transistor forming a current mirror with said amplifying transistor while a second transistor providing base currents for both of said amplifying transistor and said first transistor,

a dc bias power source coupled directly to a collector of said second transistor and coupled to a base of said second transistor through a resistor and an inductor connected in series, wherein a bypass capacitor is coupled in parallel to said resistor.

9. The power amplifier circuit of claim 8 wherein said bypass capacitor is coupled between a ground and a node between said resistor and said inductor.

10. The power amplifier circuit of claim 9 wherein said capacitor is an off-chip capacitor.

11. The power amplifier circuit of claim 9 wherein said capacitor is an adjustable capacitor.

12. The power amplifier circuit of claim 8 wherein an emitter of said second transistor is coupled to both bases of said amplifying transistor and said first transistor at a first common node.

13. The power amplifier of claim 12 wherein an emitter area ratio between said amplifying transistor and said first transistor is configured such that a quiescent current in said amplifying transistor is directly proportional to that in said first transistor.

14. The power amplifier circuit of claim 12 wherein said dc bias circuit further comprises a bias resistance coupled between said first common node and the base of said amplifying transistor, and an another resistance coupled between said first common node and the base of said first transistor.

15. The power amplifier of claim 14 wherein a resistance ratio between said bias resistor and said another resistor is configured such that a quiescent current in said amplifying transistor is directly proportional to that in said first transistor.

16. The power amplifier of claim 14 wherein both an emitter area ratio between said amplifying transistor and said first transistor and a resistance ratio between said bias resistor and said another resistor are configured such that a quiescent current in said amplifying transistor is directly proportional to that in said first transistor.

17. The power amplifier circuit of claim 8 wherein said base of said second transistor is directly coupled to a collector of said first transistor at a second common node.