Method of programming and erasing non-volatile memory cells
First Claim
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1. A method of selectively programming an individual memory cell of a non-volatile memory array, comprising:
- providing an array of memory cells each including a well of a first conductivity type, a diffusion drain of said first conductivity type encompassed by a localized well region of a second conductivity type in said well, a diffusion source of said first conductivity type laterally formed adjacent to said localized well region in said well, an isolated charge trapping layer located between said diffusion drain and diffusion source over said localized well region and said well, and a gate above said isolated charge trapping layer;
applying a first voltage, simultaneously, to said diffusion drain and said localized well region of a selected said memory cell through a selected bit line;
floating said diffusion source of said selected memory cell; and
applying a second voltage to said gate of said selected memory cell thereby inducing Fowler-Nordheim (FN) tunneling at least between said isolated charge trapping layer and said localized well region.
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Abstract
A method of selectively programming an individual memory cell of a non-volatile memory array. The non-volatile memory array is an array of memory cells. Each memory cell is made up of an ONO gate built on a substrate, which also acts as a well. On one side of the gate is a diffusion drain encompassed by a localized well region set in the well. On the other side of the gate is a diffusion source set in the well. When operated, appropriate voltages are applied to the source, the gate, the drain, and the localized well region to program or erase the non-volatile memory. The designed localized well region prevents an induction current in the unselected gates of the array, allowing for better selectivity and performance.
101 Citations
20 Claims
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1. A method of selectively programming an individual memory cell of a non-volatile memory array, comprising:
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providing an array of memory cells each including a well of a first conductivity type, a diffusion drain of said first conductivity type encompassed by a localized well region of a second conductivity type in said well, a diffusion source of said first conductivity type laterally formed adjacent to said localized well region in said well, an isolated charge trapping layer located between said diffusion drain and diffusion source over said localized well region and said well, and a gate above said isolated charge trapping layer;
applying a first voltage, simultaneously, to said diffusion drain and said localized well region of a selected said memory cell through a selected bit line;
floating said diffusion source of said selected memory cell; and
applying a second voltage to said gate of said selected memory cell thereby inducing Fowler-Nordheim (FN) tunneling at least between said isolated charge trapping layer and said localized well region. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of programming flash memory cells, comprising:
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selecting a flash memory cell including a well of a first conductivity type, a diffusion drain encompassed by a localized well region of a second conductivity type in said well, a diffusion source laterally formed adjacent to said localized well region in said well, an isolated charge trapping layer located between said diffusion drain and diffusion source over said localized well region and said well, and a gate above said isolated charge trapping layer;
applying a first voltage to said diffusion drain through a selected bit line and a second voltage to said localized well region of said selected memory cell thereby creating a depletion region at a junction of said diffusion drain and said localized well region;
grounding said diffusion source of said selected memory cell; and
applying a third voltage to said gate of said selected memory cell thereby inducing hot hole injection occurring at least between said isolated charge trapping layer and said depletion region.- View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A method of programming and erasing flash memory cells, each of the flash memory cells including a well of a first conductivity type, a diffusion drain encompassed by a localized well region of a second conductivity type in said well, a diffusion source laterally formed adjacent to said localized well region in said well, an isolated charge trapping layer located between said diffusion drain and diffusion source over said localized well region and said well, and a gate above said isolated charge trapping layer, the method comprising:
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selecting a flash memory cell and executing a programming process including the steps of;
applying a first voltage, simultaneously, to said diffusion drain and said localized well region of said selected flash memory cell through a selected bit line;
floating said diffusion source of said selected flash memory cell; and
applying a second voltage to said gate of said selected flash memory cell; and
executing an erasing process including the steps of;
floating said diffusion drain and said localized well region of said selected flash memory cell;
applying a third voltage to said diffusion source of said selected flash memory cell; and
applying a fourth voltage to said gate of said selected flash memory cell. - View Dependent Claims (15, 16, 17)
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18. A method of programming flash memory cells, comprising:
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selecting a flash memory cell including an N-well, a diffusion drain encompassed by a localized P-well region in said N-well, a diffusion source laterally formed adjacent to said localized P-well region in said N-well, an isolated charge trapping layer located between said diffusion drain and diffusion source over said localized P-well region and said N-well, and a gate above said isolated charge trapping layer;
applying a first voltage to said diffusion drain through a selected bit line and a second voltage to said localized P-well region of said selected memory cell thereby creating a depletion region at a junction of said diffusion drain and said localized P-well region;
grounding said diffusion source of said selected memory cell; and
applying a third voltage to said gate of said selected memory cell. - View Dependent Claims (19, 20)
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Specification
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Current AssigneePowerchip Semiconductor Corporation (Powerchip Technology Corporation)
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Original AssigneeEmemory Technology Inc.
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InventorsHsu, Ching-Hsiang, Yang, Ching-Sung
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Primary Examiner(s)NGUYEN, TAN
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Application NumberUS09/683,463Time in Patent Office187 DaysField of Search365/185.28, 365/185.29, 365/185.26, 365/185.18US Class Current365/185.28CPC Class CodesG11C 16/10 Programming or data input c...G11C 16/14 Circuits for erasing electr...H01L 29/792 with charge trapping gate i...H10B 69/00 Erasable-and-programmable R...
