Semiconductor memory device suitable for merging with logic

• US 6,418,067 B1
• Filed: 06/09/2000
• Issued: 07/09/2002
• Est. Priority Date: 07/12/1999
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Watanabe, Naoya, Yamazaki, Akira, Arimoto, Kazutami, Fujino, Takeshi, Hayashi, Isamu, Noda, Hideyuki
• Primary Examiner(s): Mai, Son
• Application Number:
  US09/592,454
• Time in Patent Office: 760 Days
• Field of Search: 365/200, 365/203, 365/230.03, 365/230.06
• US Class Current: 365/200
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 29/78 using programmable devices
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

Read data line pairs, write data line pairs, a spare read data line pair, and a spare write data line pair are provided extending in the column direction over a memory cell array. Spare bit repair is performed by replacing a data line pair. Column redundancy control circuit changes the timing for outputting the result of spare determination for a data write mode and for a data read mode. A semiconductor memory device suitable for merging with a logic and capable of reducing the current consumption and achieving a higher operation frequency is provided.

Claims

1. A semiconductor memory device, comprising:

a memory cell array including normal memory cells arranged in a matrix of rows and columns and spare memory cells for replacing a defective normal memory cell among said normal memory cells, a row of said spare memory cells being arranged corresponding to a row of said normal memory cells,

redundancy control circuitry for storing a defective address of said defective normal memory cell, and for determining whether a provided address signal indicating the defective address stored therein, said redundancy control circuitry outputting a result of spare determination at different timing in a data write mode and in a data read mode.

2. The semiconductor memory device according to claim 1, wherein said redundancy control circuitry includes a circuit for setting an outputting of the result of spare determination in said data write mode at an earlier timing than a timing at which the result of spare determination is output in said data read mode.

3. The semiconductor memory device according to claim 2, further comprising:

a write data bus provided extending over said memory cell array for transmitting write data to selected memory cells in said memory cell array, said write data bus including a plurality of normal write data lines for transmitting write data in parallel to a plurality of normal memory cells of said normal memory cells and a spare write data line for transmitting write data to a spare memory cell of said spare memory cells;

a read data bus provided extending over said memory cell array for transmitting read data from selected memory cells in said memory cell array, said read data bus including a plurality of normal read data lines for transmitting read data in parallel from selected normal memory cells of said normal memory cells and a spare read data line for transmitting read data from a selected spare memory cell of said spare memory cells;

write column select circuitry enabled in response to a data write instruction for connecting selected normal memory cell columns designated by said provided address signal to respective normal write data lines of said write data bus, said write column select circuitry simultaneously selecting a spare memory cell column and connecting the spare memory cell column to said spare write data line;

a read column select circuit enabled in response to a data read instruction for simultaneously reading out data from selected normal memory cell columns and a spare memory cell column designated by said provided address signal in parallel on said read data bus;

a plurality of read repair selecting circuits provided to the respective normal read data lines, each for selecting one of read data from a corresponding normal read data line and read data from said spare read data line according to the result of spare determination output from said redundancy control circuitry;

a read circuit for receiving and outputting data from said plurality of read repair selecting circuits;

a plurality of normal write circuits provided to the respective normal write data lines for transmitting write data to corresponding normal write data lines when activated;

a spare write circuit provided corresponding to said spare write data line for transmitting write data to said spare write data line when activated;

a write repair selecting circuit for selecting one of write data provided to said plurality of normal write circuits according to the result of spare determination from said redundancy control circuitry and providing selected write data to said spare write circuit, wherein

said redundancy control circuitry includes

a circuit for storing said defective address, and

a circuit for outputting a replacement instruction signal for instructing a normal read data line or a normal write data line to be replaced and a signal indicating whether to use a spare memory cell of the spare memory cells both as the result of spare determination according to said provided address signal and the stored defective address.

4. The semiconductor memory device according to claim 3, wherein timing of a column select by said read column selection circuit is earlier than timing of a column select by said write column select circuit.

5. The semiconductor memory device according to claim 3, wherein said memory cell array is divided into a plurality of row blocks along a column direction, and

the defective address storing circuit of said redundancy control circuitry circuit stores addresses of a normal read data line and a normal write data line to be replaced for predetermined number of row blocks, with said predetermined number greater than zero.

6. The semiconductor memory device according to claim 3, wherein said memory cell array is divided into a plurality of row blocks along a column direction,

said semiconductor memory device further comprises:

a plurality of sense amplifier bands provided corresponding to said plurality of row blocks and each including a plurality of sense amplifier circuits each provided corresponding to a column of a corresponding row block,

said write column select circuit includes

a write gate arranged to each column of each of said row blocks and

a plurality of write column select signal lines extending in said row direction in the sense amplifier bands and each provided in common to a column of said normal memory cells and a column of said spare memory cells, and

said read column select circuit includes

a read gate arranged corresponding to each column of each of said row blocks, and

a plurality of read column select signal lines extending in said row direction in the sense amplifier bands and each provided in common to a column of said normal memory cells and a column of said spare memory cells.

7. The semiconductor memory device according to claim 1, further comprising a plurality of write column select circuits provided corresponding to the respective normal memory cell columns and a column of said spare memory cells for electrically connecting corresponding memory cell columns to write data lines when made conductive,

each of said plurality of write column select circuits including

a write mask gate for receiving a data write mask instruction signal, and

a write column select gate connected in series to said write mask gate and made conductive in response to a column select signal.

8. The semiconductor memory device according to claim 7, further comprising a plurality of sense amplifier circuits arranged corresponding to said normal memory cell columns and the spare memory cell column for sensing and amplifying data on corresponding columns when activated, wherein

each of said plurality of write column select circuits is disposed between a corresponding sense amplifier circuit and a corresponding write data line, said write mask gate is arranged to connect to the corresponding sense amplifier circuit, and said write column select gate is arranged to connect to the corresponding write data line.

9. The semiconductor memory device according to claim 7, wherein said write data lines are provided extending in a column direction over said memory cell array,

said memory cell array is divided into a plurality of row blocks along the column direction,

each of said plurality of write column select circuits is disposed corresponding to a column of each of said row blocks, and

said column select signal is generated in response to a row block designating signal and a column address signal.

10. The semiconductor memory device according to claim 9, further comprising a write mask data line for transmitting said data write mask instruction signal, wherein said write mask data line has a first portion arranged extending in the column direction on said memory cell array and a second portion arranged extending along a row direction in which said rows extend and connected to said first portion, said second portion being coupled to said write mask gate.

11. The semiconductor memory device according to claim 10, wherein each of said row blocks is divided into a plurality of memory cell blocks along the row direction,

each of said memory cell blocks includes a plurality of sub-word lines disposed corresponding to the memory cell rows and connecting memory cells of corresponding rows,

each of said row blocks includes a main word line provided in common to corresponding memory cell blocks and a plurality of sub-word line drivers arranged corresponding to sub-word lines of said corresponding memory cell blocks each for driving to a selected state a corresponding sub-word line according to at least a signal on a corresponding main word line, and

said first portion is provided in a region for disposing the sub-word line drivers.

12. The semiconductor memory device according to claim 10, further comprising sense amplifier circuits each is arranged corresponding to a column of a corresponding row block and activated in response to a corresponding sense amplifier activating signal;

and

a logic gate for transmitting the data write mask instruction signal to said second portion according to a signal on said first portion and a sense amplifier activating signal for a corresponding sense amplifier circuit.

13. The semiconductor memory device according to claim 3, wherein each of the normal write circuits and the spare write circuit includes a write driver coupled to a corresponding write data line for two-state driving the corresponding write data line according to write data when activated, said write driver includes a bi-state buffer for outputting a two-state signal, and said corresponding write data line is constantly driven by said bi-state buffer.

14. The semiconductor memory device according to claim 7, further comprising a plurality of sense amplifier circuits arranged corresponding to the columns of said memory cells for sensing and amplifying memory cell data on corresponding column when activated, wherein said plurality of sense amplifier circuits receive a voltage from a sense power supply as an operation power supply voltage when activated, and

an amplitude of said data write mask instruction signal substantially equals a voltage value of said sense power supply.

15. The semiconductor memory device according to claim 14, wherein said write data lines include a plurality of global write data line pairs disposed extending in a column direction over said memory cell array, wherein said semiconductor memory device further comprises write circuitry for driving said plurality of global write data line pairs according to write data in said data write mode, said write circuitry operates receiving a voltage from another power supply other than said sense power supply as an operation power supply voltage.

16. The semiconductor memory device according to claim 12, wherein said logic gate receives a voltage of a same level as operation power supply voltage of the sense amplifier circuits as an operation power supply voltage to generate the data write mask instruction signal of a same amplitude as the operation power supply voltage of said sense amplifier circuits.

17. The semiconductor memory device according to claim 1, wherein said memory cell array is divided into a plurality of row blocks along a column extending direction, said semiconductor memory device further comprises:

a plurality of global write data line pairs arranged extending along the column extending direction over said memory cell array for transmitting write data in parallel;

a plurality of global read data line pairs provided separately from said plurality of global write data line pairs and extending in said column extending direction over said memory cell array for transmitting data read from selected memory cells in said memory cell array in parallel;

a plurality of sense amplifier bands arranged corresponding to said plurality of row blocks and each including a plurality of sense amplifier circuits, each sense amplifier circuit arranged corresponding to a column of a corresponding row block for sensing and amplifying data on a corresponding column;

a plurality of column select lines arranged extending in a row direction in said plurality of sense amplifier bands, each for transmitting a column select signal for selecting a column of a corresponding row block; and

a column select signal generating circuit arranged in one side in the row direction of said plurality of row blocks for driving to a selected state a column select line corresponding to an addressed column among said plurality of column select lines according to a row block designating signal and a column address signal.

18. The semiconductor memory device according to claim 16, wherein the voltage from said another power supply is a voltage provided from outside to said semiconductor memory device.

19. The semiconductor memory device according to claim 6, wherein a write column select signal provided to said write gate has a substantially same amplitude value as a value of operation power supply voltage of the sense amplifier circuit.

25. The semiconductor memory device according to claim 1, wherein said memory cell array is divided into a plurality of data path blocks each including columns of the normal memory cells and at least one column of the spare memory cells, and

said redundancy control circuit comprises a plurality of redundancy control circuits provided corresponding to the respective data path blocks, and performing the spare determination individually.

26. The semiconductor memory device according to claim 25, wherein each of said plurality of redundancy control circuits includes a program circuit for storing a defective address indicating a defective normal cell in a corresponding data path block through programming.

27. The semiconductor memory device according to claim 25, wherein

each data path block includes a predetermined number of memory blocks arranged in alignment in a column direction, and

each redundancy control circuit includes fuse groups of the predetermined number for storing a defective address indicating a defective memory cell in each respective memory block through fuse programming.

28. The semiconductor memory device according to claim 2, further comprising:

a write data bus for transmitting write data to selected memory cells in said memory cell array, said write data bus including a plurality of normal write data lines for transmitting write data in parallel to a plurality of normal memory cells of said normal cells and a spare write data line for transmitting write data to a spare memory cell of said spare memory cells;

a read data bus for transmitting read data from selected memory cells in said memory cell array, said read data bus including a plurality of normal data lines for transmitting read data in parallel from selected normal memory cells of said normal memory cells and a spare read data line for transmitting read data from a selected spare memory cell of said spare memory cells;

write column select circuitry enabled in response to a data write instruction for connecting selected normal memory cell columns designated by said provided address signal to respective normal write data lines of said write data bus, said write column select circuitry simultaneously selecting a spare memory cell column and connecting the spare memory cell column to said spare write data line;

read column select circuitry enabled in response to a data read instruction for simultaneously reading out data from selected normal cell columns and a spare memory cell column designated by said provided address signal in parallel on said read data bus;

a plurality of read repair selecting circuits provided to the respective normal read data lines, each for selecting one of read data from a corresponding normal read data line and read data from said spare read data line according to the result of spare determination output from said redundancy control circuitry;

a read circuit for receiving and outputting data from said plurality of read repair selecting circuits;

a plurality of normal write circuits provided to the respective normal write data lines for transmitting write data to corresponding normal write data lines when activated;

a spare write circuit provided corresponding to said spare write data line for transmitting write data to said spare write data line when activated;

a write repair selecting circuit for selecting one of write data provided to said plurality of normal write circuits according to the result of spare determination from said redundancy control circuit and providing selected write data to said spare write circuit;

wherein

said redundancy control circuitry includes

a circuit for storing said defective address, and

a circuit for outputting a replacement instruction signal for instructing a normal read data line or a normal write data line to be replaced and a signal indicating whether to use a spare memory cell of the spare memory cells both as the result of spare determination according to said provided address signal and the stored defective address.

20. A semiconductor memory device, comprising:

a plurality of memory cells arranged in rows and columns;

a plurality of sense amplifier circuits disposed corresponding to the columns of said memory cells, for sensing and amplifying data of memory cells of corresponding columns, said plurality of sense amplifier circuits being divided into a plurality of sense amplifier units, each of said plurality of sense amplifier units including a prescribed number of sense amplifier circuits;

a plurality of internal data lines provided corresponding to said plurality of sense amplifier units;

a plurality of column select units provided corresponding to said plurality of sense amplifier units, each for selecting a sense amplifier circuit from a corresponding sense amplifier unit in response to a column select signal;

a plurality of write mask circuits each provided corresponding to a sense block including a predetermined number of the sense amplifier units, each for inhibiting connection between a sense amplifier circuit of a corresponding sense block and a corresponding internal data line in response to a corresponding data mask instruction signal;

a plurality of write drivers provided corresponding to said plurality of internal data lines for transmitting internal write data to corresponding internal data lines when activated, said plurality of write drivers being divided into a plurality of write driver blocks corresponding to said plurality of write mask circuits; and

a plurality of mask gate circuits provided corresponding to said plurality of write mask circuits, each for applying the corresponding data mask instruction signal to a corresponding write mask circuit in response to a data mask instruction, each of the mask gate circuits including a gate circuit for activating the corresponding data mask instruction signal to inhibit connection through a corresponding write mask circuit when a corresponding write driver block is inactive.

21. The semiconductor memory device according to claim 20, wherein each of said plurality of column select units includes column select gates provided corresponding to the respective sense amplifier circuits of a corresponding sense amplifier unit, each of said column select gates is rendered conductive in response to a corresponding selected column designating signal, different selected column designating signals are applied to different column select gates in each of said column select units, and said column select signal includes said different selected column designating signals, and

each of the write mask circuits includes a write mask gate provided corresponding to each sense amplifier circuit of each sense amplifier unit of a corresponding sense block, and

the write mask gate is connected in series with a corresponding column select gate, and is rendered non-conductive when the corresponding data mask instruction signal instructs a write data masking.

22. The semiconductor memory device according to claim 20, further comprising a write driver control circuit provided corresponding to each of the write driver blocks, for activating a write driver of a corresponding write driver block in response to a data line selecting signal to transmit data from a data input circuit to a corresponding internal data line, wherein said data line selecting signal is activated individually for each write driver block, and a number of the write driver blocks to be activated at one time is determined according to an input data bit width.

23. The semiconductor memory device according to claim 22, wherein said data line selecting signal is applied in a combination of a write driver activating signal and a prescribed column address signal of at least one bit, and

the data mask instruction signal is generated by a combination of said data mask instruction and said prescribed column address signal of at least one bit.

24. The semiconductor memory device according to claim 20, wherein said plurality of internal data lines include an internal write data line for transmitting write data provided separately from an internal read data bus for transmitting data read from a memory cell, and

each of the write drivers includes a bi-state buffer for two-value driving a corresponding internal write data line, and

said bi-state buffer includes a latch circuit for latching received data, for two-value driving a corresponding internal write data line according to latched data.