Self-healing memory

• US 6,418,068 B1
• Filed: 01/19/2001
• Issued: 07/09/2002
• Est. Priority Date: 01/19/2001
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Raynham, Michael B.
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US09/766,354
• Publication Number:
  US 20020097613A1
• Time in Patent Office: 536 Days
• Field of Search: 365/200, 365/149, 365/233, 365/230.03
• US Class Current: 365/200
• CPC Class Codes: G06F 11/1088 Reconstruction on already foreseen single or plurality of spare disks
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

A memory device responsive to command signals includes multiple banks of memory arrays. Each bank includes a plurality of primary storage cells and a spare unit of spare storage cells. A detector detects an error in a first unit of the primary storage cells in a first one of the banks. A controller responsive to command signals automatically re-maps the first unit of the primary storage cells to the spare unit of storage cells, without interrupting access to memory data.

Claims

1. A self-healing volatile memory device responsive to command signals, the memory device comprising:

multiple banks of memory arrays, each bank including a plurality of primary storage cells and a spare unit of spare storage cells;

a detector for detecting an error in a first unit of the primary storage cells in a first one of the banks with no user intervention; and

a controller responsive to command signals for automatically re-mapping the first unit of the primary storage cells to the spare unit of storage cells based on the detected error.

2. The memory device of claim 1, and further comprising a mode register for storing mode information, and wherein the controller performs the remapping based on the mode information.

3. The memory device of claim 2, wherein the mode register is programmable.

4. The memory device of claim 1, wherein the memory device is a synchronous dynamic random access memory.

5. The memory device of claim 4, wherein the memory device is a double data rate synchronous dynamic random access memory.

6. The memory device of claim 1, wherein the memory arrays are organized into a plurality of rows and a plurality of columns, and wherein the spare unit of spare storage cells is a spare row of storage cells.

7. The memory device of claim 3, wherein the mode register includes a control bit, and wherein the controller performs the re-mapping when the controller receives an activate command if the control bit is set, and does not perform the re-mapping if the control bit is not set.

8. The memory device of claim 1, and further comprising a non-volatile memory for storing status information regarding the re-mapping.

9. The memory device of claim 8, wherein the status information comprises a first address identifying the first unit of primary storage cells and a second address identifying the first bank.

10. The memory device of claim 9, wherein the status information further comprises a third address identifying the spare unit of spare storage cells.

11. The memory device of claim 8, wherein the non-volatile memory is an EEPROM.

12. The memory device of claim 1, wherein the controller is responsive to command signals for re-mapping the spare unit of storage cells to the first unit of the primary storage cells.

13. The memory device of claim 1, wherein the controller performs the re-mapping for multiple banks at the same time.

14. The memory device of claim 3, wherein the mode register includes a control bit, and wherein a command directed to one of the first unit of the primary storage cells and the spare unit of storage cells is automatically directed by the controller to both the first unit of the primary storage cells and the spare unit of storage cells if the control bit is set.

15. A method of automatically self-healing a defective unit of storage cells in a volatile memory device while power is being supplied to the memory device, the method comprising:

providing a spare unit of storage cells in the memory device;

identifying the defective unit of storage cells with no user intervention;

receiving a heal command issued in response to the identified defect; and

automatically re-directing accesses directed to the defective unit of storage cells to the spare unit of storage cells based on the heal command.

16. The method recited in claim 15, and further comprising providing a mode register storing mode information, and wherein the re-directing step is performed based on the mode information.

17. The method recited in claim 16, wherein the mode register is programmable.

18. The method recited in claim 15, wherein the memory device is a synchronous dynamic random access memory.

19. The method recited in claim 15, wherein the memory device is a double data rate synchronous dynamic random access memory.

20. The method recited in claim 15, wherein the memory device includes a plurality of memory banks, each bank organized into a plurality of rows and a plurality of columns of storage cells, and wherein the spare unit of storage cells is a spare row of storage cells.

21. The method recited in claim 16, wherein the mode register includes a control bit, and wherein the re-directing step is performed when an activate command is received only if the control bit is set.

22. The method recited in claim 15, and further comprising storing status information regarding the re-directing step in a non-volatile memory.

23. The method recited in claim 22, wherein the status information comprises a first address identifying the defective unit of storage cells.

24. The method recited in claim 23, wherein the status information further comprises a second address identifying the spare unit of storage cells.

25. The method recited in claim 22, wherein the non-volatile memory is an EEPROM.

26. The method recited in claim 15, and further comprising:

receiving an unheal command; and

stopping the re-directing of accesses based on the unheal command.

27. The method recited in claim 15, wherein the memory device includes a plurality of banks of storage cells, and the re-directing step is performed for multiple banks in response to the heal command.

28. The method recited in claim 16, wherein the mode register includes a control bit, the method further comprising:

receiving a command directed to one of the defective unit of storage cells and the spare unit of storage cells;

automatically directing the command to both the defective unit of storage cells and the spare unit of storage cells if the control bit is set.