Memory device tester and method for testing reduced power states

• US 6,418,070 B1
• Filed: 09/02/1999
• Issued: 07/09/2002
• Est. Priority Date: 09/02/1999
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Hyslop, Adin E., Harrington, Matthew R., Huynh, Van C.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/388,566
• Time in Patent Office: 1,041 Days
• Field of Search: 365/201, 365/226, 365/227, 365/228, 365/229, 714/21, 714/22
• US Class Current: 365/201
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/024 in decoders
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The DRDRAM Specification suggests that the DRDRAM be put in the STBY state with no banks active. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.

Claims

1. An apparatus for testing a memory device having at least one bank, the apparatus comprising:

a control bus for coupling to the memory device;

a data bus for coupling to the memory device; and

a state machine coupled to the control bus, the state machine being configured to output a plurality of commands on the control bus, wherein at least one of the commands is adapted to cause the memory device to output a data value on the data bus regardless of whether any of the at least one banks is active.

2. The apparatus of claim 1 wherein the control bus is a column control bus, and at least one of the plurality of commands is adapted to put the memory device in a reduced power state.

3. The apparatus of claim 1 wherein the control bus is a row control bus, and at least one of the plurality of commands is adapted to put the memory device in a reduced power state.

4. The apparatus of claim 1 wherein the control bus is a column control bus, and at least one of the plurality of commands is a current calibrate (CAL) command.

5. The apparatus of claim 1 further comprising a receptacle configured to receive the memory device, wherein the receptacle is coupled to the control bus and to the data bus.

6. The apparatus of claim 1 wherein the state machine is further configured to compare the data value with an expected value.

7. The apparatus of claim 1 wherein the control bus is a row control bus, and the wherein the apparatus further comprises:

a column control bus for coupling to the memory device; and

a receptacle for receiving the memory device, wherein the receptacle is coupled to the row control bus, column control bus, and data bus.

8. The apparatus of claim 7 wherein the state machine is additionally configured to output a plurality of column commands on the column control bus, and at least one of the plurality of column commands is a current calibrate (CAL) command.

9. The apparatus of claim 8 wherein the state machine is configured to:

output on either of the row control bus or the column control bus a relax (RLX) command; and

output on the column control bus a calibration sequence comprising at least three CAL commands.

10. The apparatus of claim 1 wherein:

the memory device is a Direct Rambus Dynamic Random Access Memory; and

at least one of the plurality of commands is a relax (RLX) command which puts the Direct Rambus Dynamic Random Access Memory in a standby (STBY) state.

11. An apparatus comprising:

a memory device having multiple banks,

a control bus coupled to the memory device;

a data bus coupled to the memory device; and

a state machine coupled to the control bus, the state machine being configured to output a plurality of commands on the control bus, wherein at least one of the commands is adapted to cause the memory device to output a data value on the data bus regardless of whether any of the multiple banks are active.

12. The apparatus of claim 11 wherein the control bus is a column control bus, and at least one of the plurality of commands is adapted to put the memory device in a reduced power state.

13. The apparatus of claim 11 wherein the control bus is a row control bus, and at least one of the plurality of commands is adapted to put the memory device in a reduced power state.

14. The apparatus of claim 11 wherein the control bus is a column control bus, and at least one of the plurality of commands is a current calibrate (CAL) command.

15. A memory interface for inclusion in an application specific integrated circuit (ASIC), the memory interface comprising:

a control bus for coupling to a memory device external to the ASIC, wherein the memory device includes banks of memory cells capable of being active or inactive;

a data bus for coupling to the memory device; and

a state machine coupled to the control bus, the state machine being configured to output a plurality of commands on the control bus, wherein at least one of the commands is one which is adapted to cause the memory device to output a data value on the data bus regardless of whether any of the multiple banks are active.

16. The memory interface of claim 15 wherein the control bus is a column control bus, and at least one of the plurality of commands is adapted to put the memory device in a reduced power state.

17. The memory interface of claim 15 wherein the control bus is a row control bus, and at least one of the plurality of commands is adapted to put the memory device in a reduced power state.

18. The memory interface of claim 15 wherein the control bus is a column control bus, and at least one of the plurality of commands is a current calibrate (CAL) command.

19. The memory interface of claim 15 further comprising a receptacle configured to received the memory device, wherein the receptacle is coupled to the control bus and to the data bus.

20. The memory interface of claim 15 wherein the state machine is further configured to compare the data value with an expected value.

21. The memory interface of claim 15 wherein:

the control bus is a column control bus;

the state machine is additionally configured to output a plurality of column commands on the column control bus; and

at least one of the plurality of column commands is a current calibrate (CAL) command.

22. The memory interface of claim 21 further comprising a row control bus for coupling to the memory device, wherein the state machine is further configured to:

output on either of the row control bus or the column control bus a relax (RLX) command; and

output on the column control bus a calibration sequence comprising at least three calibrate (CAL) commands.