Method and apparatus for calibrating an IEEE-1394 cycle master

• US 6,418,150 B1
• Filed: 02/20/1998
• Issued: 07/09/2002
• Est. Priority Date: 02/20/1998
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Staats, Erik P.
• Primary Examiner(s): MARCELO, MELVIN C
• Application Number:
  US09/027,500
• Time in Patent Office: 1,600 Days
• Field of Search: 370/503, 370/516, 709/248, 713/503, 713/600
• US Class Current: 370/503
• CPC Class Codes: H04J 3/0652 Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP] bus network with centralized control in which slots are of a TDMA packet structure H04L12/4035
• CPC Class Codes: H04J 3/0655 using timestamps
• CPC Class Codes: H04L 12/40058 Isochronous transmission
• CPC Class Codes: H04L 12/40078 Bus configuration home automation networks H04L12/2803; arrangements for maintenance or administration H04L41/00
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers

Abstract

A cycle master in a digital network having a bus architecture that complies with the IEEE-1394 Standard for a High Performance Serial Bus is calibrated by first computing a clock offset representing a difference between a first time synchronized to each of a plurality of packet arrival events and a second time synchronized to periodic ones of said plurality of packet arrival events; and then adjusting a frame rate of said packet arrival events to compensate for said clock offset.

Claims

1. A method of calibrating a cycle master in a digital network, comprising the steps of:

computing a clock offset representing a difference between a first time synchronized to each of a plurality of packet arrival events and a second time synchronized to periodic ones of said plurality of packet arrival events; and

adjusting a frame rate of said packet arrival events to compensate for said clock offset.

2. The method of claim 1 wherein the step of computing a clock offset comprises computing a difference between a cycle time register value and a calibration cycle time register value.

3. A method comprising:

measuring an accuracy of a cycle timer in a digital network by measuring a cycle clock offset between a cycle clock of the cycle timer and a cycle clock of a host adapter in the network; and

adjusting a frame rate of data transmitted within the digital network according to the accuracy of the cycle timer.

4. The method of claim 3 wherein the digital network comprises a network configured in accordance with the IEEE-1394 Standard for a High Perfrmance Serial Bus.

5. The method of claim 4 wherein the data transmitted within the digital network is video data.

6. The method of claim 3 wherein a reference time of the cycle clock of the host adapter is maintained in a calibration cycle time register.

7. A system comprising:

means for synchronizing a first timer to each of a plurality of packet arrival events;

means for synchronizing a second timer not to each one but to every K of said plurality of packet arrival events, where K is a positive integer greater than one;

means for computing an offset between the first timer and the second timer; and

means for adjusting a frame rate of said packet arrival events to compensate for said offset.

8. The system of claim 7 wherein each of the packet arrival events is derived from a respective start packet in a respective frame of data.

9. The system of claim 8 wherein each frame of data includes video data.

10. The system of claim 9 further comprising:

means for display the video data.

11. A system comprising:

a transmitting device having a first timer;

a receiving device having a second timer and a third timer;

a point to point bus to be used by the transmitting and receiving devices to communicate with each other,

the transmitting device to transmit a plurality of packets into the point to point bus, each packet having a time stamp from the first timer,

the receiving device to receive each of the plurality of packets and synchronize (1) a second timer in accordance with the time stamp in each of the plurality of packets, and (2) a third timer in accordance with the time stamp that is not in each one but in every K of the plurality of packets, where K is a positive integer greater than one,

the receiving device is to compute a difference between the second timer and the third timer, and then instruct the transmitting device to adjust its packet transmission rate to compensate for the difference.

12. The system of claim 11 wherein each of the packets is a respective start packet in a respective frame of data.

13. The system of claim 12 wherein each frame of data includes video data.

14. The system of claim 13 wherein the transmitting device is a video camera and the receiving device is a display monitor.

15. The system of claim 11 wherein the transmitting device includes a cycle master, the receiving device includes a host controller, and the point to bus is according to the IEEE-1394 Standard.

16. The system of claim 11 wherein the first timer includes a first cycle time register, the second timer includes a second cycle time register, and the third timer includes a calibration cycle time register, all being updated according to essentially the same free-running clock frequency.