Automating photolithography in the fabrication of integrated circuits

• US 6,418,353 B1
• Filed: 04/22/1998
• Issued: 07/09/2002
• Est. Priority Date: 04/22/1998
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Kapoor, Ashok K., Pasch, Nicholas F., Rostoker, Michael D.
• Primary Examiner(s): Sheikh, Ayaz
• Assistant Examiner(s): Jean, Frantz B.
• Application Number:
  US09/064,802
• Time in Patent Office: 1,539 Days
• Field of Search: 700/121, 700/182, 700/95, 438/14, 438/677, 430/5, 430/30, 716/2, 716/9
• US Class Current: 700/121
• CPC Class Codes: G03F 7/70433 Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70625 Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness

Abstract

Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and. yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.

Claims

1. A computer-controlled system for optimizing device sizing in the manufacture of integrated circuits, the system comprising:

a photolithography module comprising a light source for etching wafer masks, the photolithography module having at least one operating parameter;

a wafer process for producing integrated circuits using the wafer masks produced by the photolithography module, the wafer process producing first and second updated process parameters;

a derator processor coupled to the photolithography module for combining the first updated process parameter from the wafer process with the operating parameter from the photolithography module to determine the minimum manufacturable device size that can be effectively manufactured by the wafer process;

a form factor processor coupled to the derator processor to generate circuit designs based on said minimum manufacturable device size; and

a processor coupled to the derator processor for receiving the second updated process parameter from the wafer process and transferring said second process parameter to the derator processor, thereby enabling a redetermination of the minimum manufacturable device size that can be effectively manufactured by the wafer process.

2. The system according to claim 1, further comprising means for manufacturing said integrated circuits having devices in accordance with said minimum manufacturable feature size.

3. The system according to claim 1 wherein the minimum manufacturable device size relates to optical parameters of photolithography equipment used in the manufacture of the integrated circuits.

4. The system according to claim 1 wherein the minimum manufacturable device size is determined according to the formula:

$R=\frac{\mathrm{k\lambda <br><br>}}{\mathrm{NA}}$

where R is said minimum manufacturable device size, λ

is a light source wavelength, NA is a numerical aperture value, and k is the value of a Rayleigh constant.

5. The system according to claim 1 wherein a manufacturing constant is generated from said first and second updated process parameters.

6. The system according to claim 1 wherein the at least one operating parameters includes aperture and wavelength associated with said photolithography equipment.

7. The system according to claim 1 wherein the light source is an enhanced Hg arc light and is used in the photolithography module to result in a minimum manufacturable feature size of no more than a quarter of a micron.

8. The system according to claim 1 wherein the light source is a KrF laser light and is used in the photolithography module to result in a minimum manufacturable feature size of no more than an eighth of a micron.

9. The system according to claim 1 wherein the minimum manufacturable device size is less than approximately 0.3 microns.

10. The system according to claim 1 wherein the light source is an enhanced Hg arc.

11. The system according to claim 1 wherein the form factor processor automatically generates device sizes according to the minimum manufacturable device size.

12. The system according to claim 1 wherein the second updated process parameter produced by the wafer process results from measurements taken of integrated circuit test devices contained on wafers produced by the wafer process.