Direct memory access controller and method therefor

• US 6,418,489 B1
• Filed: 01/18/2000
• Issued: 07/09/2002
• Est. Priority Date: 10/25/1999
• Status: Expired due to Term

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Mason, Kristen L., Morrison, Gary R., Polega, Jeffrey M., Tietjen, Donald L., Galloway, Frank C., Nuckolls, Charles Edward, McKeown, Jennifer L., Cohen, Robert Bradford
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): MAI, RIJUE
• Application Number:
  US09/488,368
• Time in Patent Office: 903 Days
• Field of Search: 710/1, 710/4, 710/7, 710/22, 710/23, 710/26, 710/27, 710/48, 710/54, 710/112, 710/266, 711/100, 711/105, 711/101, 711/104, 711/108, 711/111-114, 711/169
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

Direct memory access controller (DMA) (2) adapted to directly execute C language style FOR tasks, where the FOR task includes a movement of a data element from a first location to a second location in memory, and the movement is controlled by a master DMA engine (MDE) (6). A master DMA engine (MDE) (6) includes a top level state machine (52) to coordinate a context save state machine (54), a parse state machine (56), and a running state machine (58). An loop control descriptor (LCD) queue (74) and a data routing descriptor (DRD) cache store information. The LCD queue allows pipelining of descriptor parsing, while the DRD cache avoids refetching of DRDs on reentry of loops.

Claims

1. In a data processing system having a processor, a memory and a direct memory access controller, the direct memory access controller having a plurality of execution units, the direct memory access controller adapted to directly execute FOR tasks assigned by the processor, method for controlling the direct memory access controller, comprising the steps of:

saving context information for a task, comprising;

storing a loop nest pointer value from a loop nest pointer register to a first memory location, the loop nest pointer value corresponding to a last loop control descriptor at a predetermined nest level;

storing a current pointer value from a current pointer register to a second memory location, the current pointer value corresponding to a next data routing descriptor to be executed on restoration of the task; and

storing context information for at least one execution unit to a third memory location; and

restoring the context information for the task, comprising;

determining if the at least one execution unit context information has changed;

if the at least one execution unit context information has changed, writing the stored context information from the third memory location to at least one register in the at least one execution unit;

writing the stored loop nest pointer value from the first memory location to the loop nest pointer register; and

writing the stored current pointer value from the second memory location to the current pointer register.

2. The method as in claim 1, further comprising the steps of:

executing a FOR task having a first loop; and

storing a first set of variable values for variables associated with initialization of the first loop in a cache.

3. The method as in claim 2, wherein the FOR task comprises a second loop, the method further comprising the step of:

storing a second set of variable values for variables associated with initialization of the second loop in the cache.

4. In a data processing system having a processor, a memory and a direct memory access controller, the direct memory access controller adapted to directly execute FOR tasks assigned by the processor, said task comprising a movement of a data element from a first location in said memory to a second location in said memory, each of the FOR tasks, the direct memory access controller comprising:

a first in first out queue for pipelining interpretation and fetching of loop control descriptors, wherein loop control descriptors are stored sequentially in the queue according to occurrence in a FOR task; and

a pointer identifying a next location in the queue for storing a next loop control descriptor.

5. The direct memory access controller of claim 4, further comprising:

a cache for storing data routing descriptors, wherein the data routing descriptors are stored according to a top-loading scheme.

6. The direct memory access controller of claim 5, further comprising:

a base address register storing base addresses corresponding to the data routing descriptors, wherein each entry in the base address register stores a portion of the address, and wherein each entry in the base address register includes a boundary identification bit to identify the address.

7. The data processing system of claim 4, wherein the direct memory access controller further comprises a variable cache, the variable cache having a plurality of entries for storing variable values, the variable values being used to initialize FOR-task loop index variables.

8. The data processing system of claim 7, wherein the variable cache is fully associative.

9. The data processing system of claim 7, wherein the plurality of entries of the variable cache are allocated and replaced sequentially.

10. The data processing system of claim 7, wherein each value stored in the variable cache is unique.

11. The data processing system of claim 7, wherein a first portion of the plurality of entries of the variable cache are read in parallel, wherein the first portion of the plurality of entries stores variables to initialize loop indices associated with a first FOR-task loop.

12. In a data processing system having a processor, a memory and a direct memory access controller, the direct memory access controller adapted to directly execute FOR tasks assigned by the processor, said task comprising a movement of a data element from a first location in said memory to a second location in said memory, each of the FOR tasks described by at least one loop control descriptor and at least one data flow representation of a loop body, the direct memory access controller comprising:

a top-loading cache having a plurality of entries, the cache for storing data flow representations of FOR task bodies, nest level information corresponding to the data flow representations, address offset information for the data flow representations; and

a pointer identifying a next location in the cache for storing a next data flow representations and corresponding valid bits.

13. The direct memory access controller of claim 12, wherein the address offset information stored in the cache includes a base address select bit, the direct memory access controller further comprising:

a first base address register selected when the base address select bit is a first value; and

a second base address register selected when the base address select bit is a second value;

wherein the selected one of the first and second base address registers combined with the address offset information identifies a storage location of each data flow representation.

14. The direct memory access controller of claim 12, further comprising:

a first in first out queue for pipelining interpretation and fetching of loop control descriptors, wherein loop control descriptors are stored sequentially in the queue according to occurrence in a FOR task; and

a pointer identifying a next location in the queue for storing a next loop control descriptor.

15. The direct memory access controller of claim 12, further comprising:

a memory interface unit having a plurality of buffers, the memory interface unit adapted to receive control signals via a communication bus;

wherein a first one of the control signals identifies a transaction as a cacheable transaction.

16. The direct memory access controller of claim 15, wherein in response to the first one of the control signals identifying a first transaction as a cacheable transaction, the buffers cache data;

and

wherein in response to a the first one of the control signals identifying a second transaction as a non-cacheable transaction, the buffers store data individually.

17. The direct memory access controller of claim 15, wherein in response to a second of the control signals, at least a portion of the plurality of buffers are marked to write out data.

18. The direct memory access controller of claim 12, further comprising:

a memory interface unit having a plurality of buffers, wherein the FOR tasks information is utilized to control the plurality of buffers.