Accurate timing calibration for each of multiple high-speed clocked receivers using a single DLL

• US 6,418,537 B1
• Filed: 07/08/1999
• Issued: 07/09/2002
• Est. Priority Date: 12/07/1997
• Status: Expired due to Term

• Current Assignee: MACOM Technology Solutions Holdings, Inc.
• Original Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Inventors: Yang, Kewei, Lin, Feng Cheng
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US09/350,414
• Time in Patent Office: 1,097 Days
• Field of Search: 713/400, 713/401, 713/503, 327/141, 327/155, 327/156, 327/158, 327/161, 375/200, 375/316, 375/354
• US Class Current: 713/400
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0822 Copy directories local copy tags for implementing a bus snooping protocol G06F12/0831
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring
• CPC Class Codes: G06F 3/00 Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

In a preferred embodiment, the invention uses an 8-to-1 data serialization circuit in the transmitter to convert 80-bit parallel 200 MHz data to 10-bit parallel 1.6 Mb/s date. On the receiver side, data are captured using a forwarded clock and de-serialized. A single global DLL generates 16 master phases without reference to the word boundaries of data being transmitted. These 16 unreferenced phases are input to a phase rotator that, via a series of calibration steps, maps the unreferenced phases into named phases, and in doing so references the phases to the word boundary of the data being transmitted over the slowest data line of the parallel channel. The named phases are then input to a data interpolator in each receiver, which generates 16 local phases. The 16 local phases correspond to the data-bit centers and data-bit edges for each of the 8 bits transferred per major channel clock period. In a bit-centering calibration step, a training pattern is evaluated by each receiver and each data interpolator dynamically adjusts a delay applied to the 16 local phases to establish the local center-data phases in the center of the bits received by the corresponding receiver. In an additional calibration step, on a per-wire basis, 8 contiguous bits are selected as the data outputs from a 10-bit window. The local center-data phases are used to serialize and de-serialize the channel data for the receiver. The present invention optimizes clock timing for each channel bit, thus providing the benefits of a dedicated DLL per channel bit, without the associated cost.

Claims

1. A method of retrieving data transmitted over a communications channel, the method comprising:

providing a Delay Locked Loop (DLL);

generating a first plurality of unreferenced master phases using the DLL;

mapping the unreferenced phases into named phases to reference the named phases to word boundaries of the data transmitted;

generating a first plurality of local phases, including center-data phases and edge-data phases that correspond to data-bit centers and data-bit edges for each of a second plurality of bits transmitted per major channel clock period;

dynamically adjusting a delay applied to the first plurality of local phases to establish a second plurality of local center-data phases in a center of the second plurality of bits received by a corresponding receiver; and

serializing and de-serializing the channel data for the receiver using the center-data phases.

2. A method of operating receive circuitry coupled to a parallel channel comprising parallel data lines and a parallel clock line, wherein the parallel data lines transfer calibration signals and data signals, wherein the parallel clock line transfers clock signals, wherein the receive circuitry comprises a plurality of receivers that are each coupled to one of the parallel data lines, the method comprising:

processing the clock signals to generate a plurality of master phases;

referencing the master phases to word boundaries in the data signals;

in each of the receivers, processing the master phases to generate local phases;

in each of the receivers, processing the calibration signals to adjust the local phases; and

in each of the receivers, de-serializing the data signals using the adjusted local phases.

3. The method of claim 2 wherein processing the clock signal to generate the plurality of master phases comprises using a single delay locked loop for all of the receivers on the parallel channel.

4. The method of claim 2 wherein referencing the master phases to the word boundaries in the data signals comprises referencing the master phases to the word boundaries on the slowest of the parallel data lines.

5. The method of claim 2 wherein processing the calibration signals to adjust the local phases comprises processing the calibration signals to adjust the local phases to local center-data phases.

6. The method of claim 2 wherein the master phases include an edge phase and a center phase for each bit in the calibration signals.

7. The method of claim 2 wherein the calibration signals are processed to adjust the local phases every clock period.

8. The method of claim 2 wherein the calibration signals comprise the pattern “

10100111”

.

9. Receive circuitry coupled to a parallel channel comprising parallel data lines and a parallel clock line, wherein the parallel data lines transfer calibration signals and data signals, and wherein the parallel clock line transfers clock signals, the receive circuitry comprising:

clock circuitry configured to process the clock signals to generate a plurality of master phases and to reference the master phases to word boundaries in the data signals; and

a plurality of receivers that are each coupled to one of the parallel data lines wherein each of the receivers is configured to process the master phases to generate local phases, process the calibration signals to adjust the local phases, and de-serialize the data signals using the adjusted local phases.

10. The receive circuitry of claim 9 wherein the clock circuitry comprises a single delay locked loop for all of the receivers on the parallel channel and the delay locked loop is configured to generate the plurality of master phases.

11. The receive circuitry of claim 9 wherein the clock circuitry is configured to reference the master phases to the word boundaries on the slowest of the parallel data lines.

12. The receive circuitry of claim 9 wherein the receivers are each configured to process the calibration signals to adjust the local phases to local center-data phases.

13. The receive circuitry of claim 9 wherein the master phases include an edge phase and a center phase for each bit in the calibration signals.

14. The receive circuitry of claim 9 wherein the receivers are each configured to process the calibration signals to adjust the local phases every clock period.

15. The receive circuitry of claim 9 wherein the calibration signals comprise the pattern “

10100111”

.