Integrated circuits and methods for their fabrication

• US 6,420,209 B1
• Filed: 03/29/2000
• Issued: 07/16/2002
• Est. Priority Date: 10/29/1996
• Status: Expired due to Term

• Current Assignee: Invensas Corporation
• Original Assignee: Tru-Si Technologies, Inc.
• Inventors: Siniaguine, Oleg
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Dang, Phuc T.
• Application Number:
  US09/538,869
• Time in Patent Office: 839 Days
• Field of Search: 438/15, 438/107, 438/108, 438/109, 438/113, 438/114, 438/209, 438/455, 438/458, 438/974, 438/977, 438/187, 438/335, 438/462, 438/975
• US Class Current: 438/108
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/482 consisting of lead-in layers inseparably applied to the semiconductor body electrodes H01L29/40
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the metal is exposed. When the etch exposes the insulator at the via bottoms, the insulator is etched slower than the wafer material (e.g. silicon). Therefore, when the dielectric is etched off and the metal is exposed, the dielectric protrudes down from the wafer back side around the exposed metal contact pads, by about 8 μm in some embodiments. The protruding dielectric portions improve insulation between the wafer and the contact pads when the contact pads are soldered to an underlying circuit. In some embodiments, before the contact pads are soldered, additional dielectric is grown on the wafer back side without covering the contact pads. In some embodiments, the wafer etch and the fabrication of the additional dielectric are performed one after another by a plasma process while the wafer is held in a non-contact wafer holder. In some embodiments, the wafer is diced and the dice are tested before the etch. The etch and the deposition of the additional dielectric are performed on good dice only. In some embodiments, the dice are not used for vertical integration.

Claims

1. A method for manufacturing a vertical integrated circuit, the method comprising:

(1) manufacturing a plurality of individual integrated circuits, wherein manufacturing of at least one of the individual integrated circuits comprises;

manufacturing an integrated circuits in a wafer;

separating the integrated circuit from the wafer;

performing a back side etch of the integrated circuit separated from the wafer to thin the integrated circuit as the integrated circuit is held in a non-contact wafer holder;

(2) after the manufacture of the individual integrated circuits has been completed, and each individual integrated circuit has been manufactured to its final thickness, attaching the individual integrated circuits to each other to form a vertical integrated circuit.

2. A method for integrated circuit fabrication, the method comprising:

fabricating a plurality of integrated circuits from a semiconductor wafer;

dicing the wafer into dice; and

thinning one or more dice which were obtained from the wafer in said dicing as the one or more dice are held in a non-contact holder.

3. The method of claim 2 wherein fabricating a plurality of integrated circuits comprises fabricating one or more circuit elements in or over a first side of the wafer, wherein each die has a first side located at the first side of the wafer;

and

wherein during the thinning process, the first side of each of the one or more dice faces the non-contact holder which protects one or more of the circuit elements fabricated in or over the first sides of the one or more dice from being etched.

4. The method of claim 2 wherein the etching process comprises a fluorine containing plasma etch at atmospheric pressure.

5. The method of claim 2 wherein the wafer comprises silicon.

6. The method of claim 2 wherein the thinning of the one or more dice is preceded by testing of the integrated circuits, and the thinning is performed only on a die or dice that have passed the test.

7. The method of claim 2 wherein manufacturing each of the individual integrated circuits comprises:

manufacturing an integrated circuit in a wafer;

separating the integrated circuit from the wafer;

performing a back side etch of the integrated circuit separated from the wafer to thin the integrated circuit as the integrated circuit is held in a non-contact wafer holder.