Three-dimensional memory array and method of fabrication

• US 6,420,215 B1
• Filed: 03/21/2001
• Issued: 07/16/2002
• Est. Priority Date: 04/28/2000
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Johnson, Mark, Knall, N. Johan
• Primary Examiner(s): Thompson, Craig
• Application Number:
  US09/814,727
• Publication Number:
  US 20020088998A1
• Time in Patent Office: 482 Days
• Field of Search: 438/131, 438/128-130, 438/132, 438/197, 438/210, 438/600, 438/601
• US Class Current: 438/131
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only

Abstract

A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally the diode is located in one rail-stack and the other half in the other rail-stack.

Claims

1. A method for fabricating a multi-level memory array comprising the steps of:

depositing a metal layer;

forming at least one layer of silicon on the metal layer where the silicon is doped with a first conductivity type dopant;

masking and etching the silicon and metal layers to define a plurality of parallel, spaced-apart rail-stacks;

filling the space between the rail-stacks with a dielectric material;

planarizing the silicon layer and the dielectric material to form a planarized surface, and

forming a layer of material for an antifuse on the planarized surface.

2. The method defined by claim 1, wherein the layer of antifuse material comprises a dielectric.

3. The method defined by claim 1 wherein the layer of antifuse metal comprises undoped silicon.

4. The method defined by claim 1 wherein the layer of antifuse material is grown on the rail-stacks.

5. The method defined by claim 1 wherein the layer of antifuse material is a blanket deposition on the rail-stacks and filling material.

6. The method defined by claim 2 wherein the silicon layer comprises a first silicon heavily doped with an n-type dopant and a second layer more lightly doped with the n-type dopant.

7. The method defined by claim 2 wherein the silicon layer is a heavily doped layer.

8. The method defined by claim 7 wherein the antifuse layer is approximately 80-200 Å

thick and comprises silicon dioxide.

9. A method for fabricating a multi-level memory array comprising the steps of:

forming a metal layer;

forming a first silicon layer heavily doped with a first conductivity type dopant on the metal layer;

depositing a second silicon layer on the first silicon layer, the second silicon layer being more lightly doped than the first layer with the first conductivity type dopant;

forming a layer of an antifuse material on the second silicon layer;

depositing a third silicon layer on the layer of antifuse material heavily doped with a second conductivity type dopant;

defining spaced-apart rail-stacks from the conductive layer, first and second silicon layers, the layer of antifuse material and third silicon layer;

filling space between the rail-stacks with a dielectric, and

planarizing the upper surface of the dielectric fill and the third silicon layer.

10. A method for fabricating a multi-level memory array comprising the steps of:

forming a conductor layer;

forming a first silicon layer doped with a first conductivity type dopant on the conductive layer;

forming a second silicon layer on the first silicon layer, the second silicon layer being more lightly doped than the first layer with the first conductivity type dopant;

forming a layer of an antifuse material on the second silicon layer;

forming a third silicon layer on the layer of antifuse material doped with a second conductivity type dopant;

defining spaced-apart first rail-stacks from the conductive layer, the first and second silicon layers, the layer of antifuse material and the third silicon layer;

filling between the first rail-stacks with a dielectric, and

planarizing the upper surface of the dielectric fill and the third silicon layer.

11. The method defined by claim 10 wherein the layer of antifuse material is an oxide grown on the second silicon layer.

12. The method defined by claim 11 wherein the layer of antifuse material is a deposited dielectric.

13. The method of claim 10 including repeating the steps of claim 75 to form second rail-stacks disposed above the first rail-stacks perpendicular to the first rail-stacks.

14. The method defined by claim 13 including additionally etching through the third silicon layer of the first rail-stacks in alignment with the second rail-stacks.

18. The method defined in claim 13 wherein the second silicon layer is approximately 300-3000 Å

thick.

19. The method defined in claim 13 wherein the third silicon layer is approximately 300-2000 Å

thick after planarization.

20. The method defined by claim 13 wherein the antifuse layer is a silicon dioxide layer with a thickness of approximately <

200 Å

thick.

21. The method defined by claim 13 wherein the antifuse layer is a grown silicon dioxide layer grown from the third silicon layer.

22. The method defined by claim 13 wherein the antifuse layer is a silicon nitride layer.

15. A method for fabricating a multi-level memory array comprising the steps of:

forming a first silicon layer lightly doped with a first conductivity type dopant;

forming a second silicon layer more heavily doped than the first layer with the first conductivity type dopant;

depositing a conductive layer on the second silicon layer;

depositing a third silicon layer heavily doped with a second conductivity type dopant;

etching the first, second and third silicon layers and conductive layers to define a plurality of parallel, spaced-apart rail-stacks;

filling the space between the rail-stacks with a dielectric material;

planarizing the third silicon layer and the dielectric filling material, and

depositing a layer of an antifuse material on the planarized surface.

16. The method defined by claim 15 wherein the conductive layer is approximately 500-1,500 Å

thick.

17. The method defined in claim 15 wherein the first silicon layer is 1000-4000 Å

thick.