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Method for the production of a DRAM cell configuration

  • US 6,420,228 B1
  • Filed: 05/08/2001
  • Issued: 07/16/2002
  • Est. Priority Date: 05/02/1997
  • Status: Expired due to Term
First Claim
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1. A method for the production of a DRAM cell configuration, which comprises:

  • producing memory cells each having a read-out transistor and a storage capacitor with a storage node;

    producing bit and word lines;

    forming the read-out transistor as a vertical MOS transistor integrated in a substrate of semiconductor material;

    providing the MOS transistor with two first source/drain regions each belonging to a further, adjacent vertical MOS transistor, disposed separately one after the other along the bit line and adjoining the bit line, two second source/drain regions each connected to the storage node;

    producing two channel regions;

    producing a gate oxide adjoined by the two channel regions;

    producing a gate electrode between the two channel regions;

    adjoining exactly two opposite sides of the gate electrode with the gate oxide;

    electrically connecting the gate electrodes of adjacent MOS transistors along the word line; and

    placing the gate electrode and the storage node one under the other.

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