Method for the production of a DRAM cell configuration

• US 6,420,228 B1
• Filed: 05/08/2001
• Issued: 07/16/2002
• Est. Priority Date: 05/02/1997
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Roesner, Wolfgang, Hofmann, Franz, Risch, Lothar
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US09/851,051
• Time in Patent Office: 434 Days
• Field of Search: 438/243-249, 438/386-392, 438/242
• US Class Current: 438/244
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A DRAM cell configuration includes a vertical MOS transistor per memory cell. First source/drain regions of the transistor each belong to two adjacent transistors and adjoin a bit line. Second source/drain regions of the transistor are connected to a storage node. A gate electrode of the transistor has exactly two sides adjoined by a gate oxide. The DRAM cell configuration can be produced by using three masks with a memory cell area of 4 F². F is a minimum structure size which can be produced by using the respective technology.

Claims

1. A method for the production of a DRAM cell configuration, which comprises:

producing memory cells each having a read-out transistor and a storage capacitor with a storage node;

producing bit and word lines;

forming the read-out transistor as a vertical MOS transistor integrated in a substrate of semiconductor material;

providing the MOS transistor with two first source/drain regions each belonging to a further, adjacent vertical MOS transistor, disposed separately one after the other along the bit line and adjoining the bit line, two second source/drain regions each connected to the storage node;

producing two channel regions;

producing a gate oxide adjoined by the two channel regions;

producing a gate electrode between the two channel regions;

adjoining exactly two opposite sides of the gate electrode with the gate oxide;

electrically connecting the gate electrodes of adjacent MOS transistors along the word line; and

placing the gate electrode and the storage node one under the other.

2. The method according to claim 1, which comprises:

forming the substrate with a first layer doped by a first conductivity type, a second layer doped by a second conductivity type opposite to the first conductivity type, and a third layer doped by the first conductivity type and adjoining a surface of the substrate;

producing first trenches in strip form running substantially parallel and cutting through the third layer, by etching with a first mask;

producing second trenches each running in strip form and substantially parallel, cutting through the third layer, crossing the first trenches in crossover regions and being shallower in the crossover regions than in regions in between;

producing the first source/drain regions as remaining parts of the third layer;

partially providing the first trenches with insulating material electrically insulating the first and second source/drain regions of adjacent MOS transistors from one another along the word line;

providing the second trenches with capacitor dielectrics, the storage nodes, the gate oxides and the gate electrodes; and

applying the bit lines to the surface transversely relative to the word lines with a mask, causing the first source/drain regions to adjoin the bit lines.

3. The method according to claim 2, which comprises:

initially forming the storage nodes and then the gate electrodes;

initially producing a first insulation structure on the second trenches to form the storage nodes, for surrounding the second trenches on all sides with insulating material;

forming the storage nodes, after the production of the first insulation structure, by providing the second trenches with a material doped by the first conductivity type up to a first level above an interface between the first layer and the second layer and below an interface between the second layer and the third layer;

additionally forming the storage nodes by subsequently removing part of the first insulation structure between the first level and the surface, to form a capacitor dielectric;

additionally forming the storage nodes by subsequently providing the second trenches with a material doped by the first conductivity type up to a second level above the first level and below the interface between the second layer and the third layer;

producing a gate oxide before forming the gate electrode;

subsequently forming the gate electrode by filling the second trenches with a conductive material up to a third level above the interface between the second layer and the third layer, for additionally producing the word line;

filling the second trenches with insulating material up to the surface after the formation of the gate electrodes; and

forming the second source/drain regions by outdiffusion of dopant of the storage node into the second layer.

4. The method according to claim 3, which comprises:

forming the first trenches by producing and structuring a first SiO₂ layer with photolithographic processes, for uncovering semiconductor material;

removing remaining parts of the first SiO₂ layer before the bit lines are produced;

forming the second trenches by depositing SiO₂ for filling the first trenches, and subsequently selectively etching SiO₂ relative to semiconductor material with photolithographic processes, for uncovering semiconductor material in regions located between the crossover regions;

forming the second trenches by etching semiconductor material, after the semiconductor material has been uncovered in the regions located between the crossover regions;

filling the second trenches with material up to the first level, the second level and the third level and up to the surface in each case by deposition of the material, for completely filling the second trenches, and respective subsequent etching of the material down to the first level, the second level, the third level, and the surface.

5. The method according to claim 4, which comprises:

forming the first trenches by depositing a silicon nitride layer over the whole area before the SiO₂ layer is produced;

additionally forming the first trenches by structuring the SiO₂ layer and the silicon nitride layer with photolithographic processes, for uncovering semiconductor material; and

removing remaining parts of the silicon nitride layer before the bit lines are produced.