Coupled multilayer soft magnetic films for high frequency microtransformer for system-on-chip power supply

• US 6,420,954 B1
• Filed: 01/04/2000
• Issued: 07/16/2002
• Est. Priority Date: 12/10/1999
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): MAI, ANH T
• Application Number:
  US09/477,407
• Time in Patent Office: 924 Days
• Field of Search: 438/401, 438/402, 438/424, 336/200, 336/223, 336/218, 336/232, 257/390, 257/692
• US Class Current: 336/232
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 19/04 Transformers or mutual inductances suitable for handling frequencies considerably beyond the audio range resonant circuits H03H
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 41/046 structurally combined with ferromagnetic material
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind

Abstract

A microtransformer for a high-performance system-on-chip power supply is disclosed. Through-wafer openings in a substrate allow the primary and secondary wiring on both surfaces of the silicon substrate. An insulating silicon oxide layer is first deposited on all surfaces of the substrate. A magnetic film is further deposited on the silicon oxide layer followed by the application of another insulating layer. Coils are fabricated next by patterned deposition on both sides of the substrate and through the holes. The coils can be, e.g., single coils or primary or secondary coils of a transformer structure, with secondary having one or more output taps to supply different output voltages. For better flux closure, various magnetic layers and insulators can be deposited on top of the windings. For even a better flux closure, the various magnetic layers can be coupled.

Claims

1. An electromagnetic element comprising:

a substrate with at least a first and second through-holes that define between them a coil winding area that includes a top surface of said substrate, a bottom surface of said substrate, and side surfaces of said through-holes;

a first layer of magnetic material provided on said substrate in said coil winding area;

a first layer of electrically conductive material forming at least one coil winding provided on said substrate in said coil winding area; and

a second layer of magnetic material formed over said first layer of electrically conductive material, said second layer of magnetic material being connected with said first layer of magnetic material.

2. The electromagnetic element of claim 1, wherein said conductive material is copper or an alloy of copper.

3. The electromagnetic element of claim 1, wherein said conductive material is aluminum or an alloy of aluminum.

4. The electromagnetic element of claim 1, wherein said first layer of electrically conductive material forms two coil windings.

5. The electromagnetic element of claim 4, wherein said electromagnetic element is a transformer and said two coil windings form the primary and secondary coil windings of said transformer.

6. The electromagnetic element of claim 1 further comprising a first insulating layer between said substrate and said first layer of magnetic material.

7. The electromagnetic element of claim 6, wherein said first insulating layer is formed of a high temperature polymer film.

8. The electromagnetic element of claim 7, wherein said high temperature polymer film is a polyimide.

9. The electromagnetic element of claim 6, wherein said first insulating layer is formed of an oxide or a nitride.

10. The electromagnetic element of claim 6, wherein said first insulating layer has a thickness of 0.5 to 1 μ

m.

11. The electromagnetic element of claim 6 further comprising a second insulating layer between said first layer of magnetic material and said first layer of electrically conductive material.

12. The electromagnetic element of claim 11, wherein said second insulating layer is formed of a high temperature polymer film.

13. The electromagnetic element of claim 12, wherein said high temperature polymer film is a polyimide.

14. The electromagnetic element of claim 11, wherein said second insulating layer is formed of an oxide or a nitride.

15. The electromagnetic element of claim 11, wherein said second insulating layer has a thickness of 0.5 to 1 μ

m.

16. The electromagnetic element of claim 11 further comprising a third insulating layer between said first layer of electrically conductive material and said second layer of magnetic material.

17. The electromagnetic element of claim 16, wherein said third insulating layer is formed of a high temperature polymer film.

18. The electromagnetic element of claim 17, wherein said high temperature polymer film is a polyimide.

19. The electromagnetic element of claim 16, wherein said third insulating layer is formed of an oxide or a nitride.

20. The electromagnetic element of claim 16, wherein said third insulating layer has a thickness of 0.5 to 1 μ

m.

21. The electromagnetic element of claim 16 further comprising a second layer of electrically conductive material forming at least one coil on said second layer of magnetic material.

22. The electromagnetic element of claim 21 further comprising an insulating layer between said second layer of magnetic material and said second layer of electrically conductive material.

23. The electromagnetic element of claim 21, wherein said second layer of conductive material is copper or an alloy of copper.

24. The electromagnetic element of claim 21 wherein said second layer of conductive material is aluminum or an alloy of aluminum.

25. The electromagnetic element of claim 21, wherein said second layer of electrically conductive material forms two coils.

26. The electromagnetic element of claim 21 further comprising a top protective insulating layer over said second layer of electrically conductive material.

27. The electromagnetic element of claim 26 further comprising a passivating layer over said top protective insulating layer.

28. The electromagnetic element of claim 1, wherein said first layer of magnetic material is made of Fe—

X—

N alloy or Fe—

X—

B—

N alloy, wherein X is at least one atom selected from the group consisting of Zr, Hf, Ti, Nb, Ta, V, Mo, W, and Cr.

29. The electromagnetic element of claim 28, wherein said first layer of magnetic material is further formed of a plurality of thin soft magnetic layers and at least one insulating spacer layer formed between said thin soft magnetic layers.

30. The electromagnetic element of claim 29, wherein said insulating spacer layer is formed of a material selected form the group consisting of Permalloy (NiFe), NiFeMo, Co—

Zr, CoZrRe, CoFeSiB, CoNbZr, and Co—

Cr—

O granular films.

31. The electromagnetic element of claim 1, wherein said second layer of magnetic material is made of Fe—

X—

N alloy or Fe—

X—

B—

N alloy, wherein X is at least one atom selected from the group consisting of Zr, Hf, Ti, Nb, Ta, V, Mo, W, and Cr.

32. The electromagnetic element of claim 21, wherein said second layer of magnetic material is further formed of a plurality of thin soft magnetic layers and at least one insulating spacer layer formed between said thin soft magnetic layers.

33. The electromagnetic element of claim 32, wherein said insulating spacer layer is formed of a material selected form the group consisting of Permalloy (NiFe), NiFeMo, Co—

Zr, CoZrRe, CoFeSiB, CoNbZr, and Co—

Cr—

O granular films.

34. The electromagnetic element of claim 1 further comprising a top protective insulating layer over said second layer of magnetic material.

35. The electromagnetic element of claim 34 further comprising a passivating layer over said top protective insulating layer.

36. The electromagnetic element of claim 1, wherein said substrate is a semiconductor substrate.

37. The electromagnetic element of claim 36, wherein said semiconductor substrate is a silicon substrate.

38. The electromagnetic element of claim 36, wherein said semiconductor substrate is a germanium substrate.

39. The electromagnetic element of claim 36, wherein said semiconductor substrate is a gallium arsenide substrate.

40. The electromagnetic element of claim 1, wherein said substrate is a ceramic substrate.

41. The electromagnetic element of claim 1, wherein said substrate is a quartz substrate.

42. The electromagnetic element of claim 1, wherein said substrate is an Al₂O₃/TiC substrate.

43. The electromagnetic element of claim 1, wherein said electromagnetic element is selected from the group consisting of a microtransformer and a microinductor.

44. The electromagnetic element of claim 1, wherein said semiconductor substrate further contains circuitry for a DC-DC converter.

45. The electromagnetic element of claim 44, wherein said semiconductor substrate further contains circuitry for a power supply which includes said DC-DC converter.

46. A method for fabricating a microtransformer comprising the steps of:

providing a substrate with at least a first and second through-holes that define between them a coil winding area that includes a top surface of said substrate, a bottom surface of said substrate, and side surfaces of said through-holes;

forming a first layer of magnetic material on said substrate in said coil winding area;

forming a first layer of electrically conductive material forming at least one coil winding on said substrate in said coil winding area; and

forming a second layer of magnetic material over said first layer of electrically conductive material, said second layer of magnetic material being connected with said first layer of magnetic material.

47. The method of claim 46, wherein said first layer of electrically conductive material has two coils.

48. The method of claim 46 further comprising the step of providing a first insulating layer between said first layer of magnetic material and said substrate.

49. The method of claim 48 further comprising the step of providing a second insulating layer between said first layer of magnetic material and said first layer of electrically conductive material.

50. The method of claim 49 further comprising the step of providing a third insulating layer between said first layer of electrically conductive material and said second layer of magnetic material.

51. The method of claim 50 further comprising the step of providing a top protective insulating layer over said second layer of magnetic material.

52. The method of claim 51 further comprising the step of providing a passivating layer over said top protective insulating layer.

53. The method of claim 46 further comprising the step of forming a second layer of electrically conductive material forming at least one coil on said second layer of magnetic material.

54. The method of claim 53 further comprising the step of forming an insulating layer between said second layer of magnetic material and said second layer of electrically conductive material.

55. The method of claim 53 further comprising the step of providing a top protective insulating layer over said second layer of electrically conductive material.

56. The method of claim 55 further comprising the step of providing a passivating layer over said top protective insulating layer.

57. The method of claim 46, wherein said substrate is a semiconductor substrate.

58. The method of claim 57, wherein said semiconductor substrate is a silicon substrate.

59. The method of claim 57, wherein said semiconductor substrate is a germanium substrate.

60. The method of claim 57, wherein said semiconductor substrate is a gallium arsenide substrate.

61. The method of claim 46, wherein said substrate is a ceramic substrate.

62. The method of claim 46, wherein said substrate is a quartz substrate.

63. The method of claim 46, wherein said substrate is an Al₂O₃/TiC substrate.

64. A system-on-chip comprising:

a substrate having a through-hole microtransformer formed thereon, wherein said through-holes microtransformer is formed in a coil winding area defined by first and second through-holes in said substrate, said coil winding area including a top surface of said substrate, a bottom surface of said substrate, and side surfaces of said through-holes, said microtransformer further comprising a first layer of magnetic material provided on said substrate in said coil winding area, a first layer of electrically conductive material forming at least one coil winding provided on said substrate in said coil winding area, and a second layer of magnetic material formed over said first layer of electrically conductive material, said second layer of magnetic material being connected with said first layer of magnetic material; and

at least one integrated circuit chip attached to said substrate and electrically connected to said substrate.

65. The system-on-chip of claim 64, wherein said layer of electrically conductive material forms two coil windings.

66. The system-on-chip of claim 65, wherein said two coil windings form a primary and secondary coil windings of said microtransformer.

67. The system-on-chip of claim 64, wherein said microtransformer further comprises a first insulating layer between said substrate and said first layer of magnetic material.

68. The system-on-chip of claim 67, wherein said microtransformer further comprises a second insulating layer formed between said first layer of magnetic material and said first layer of electrically conductive material.

69. The system-on-chip of claim 68, wherein said microtransformer further comprises a third insulating layer between said first layer of electrically conductive material and said second layer of magnetic material.

70. The system-on-chip of claim 69, wherein said microtransformer further comprises a top protective insulating layer over said second layer of magnetic material.

71. The system-on-chip of claim 70, wherein said microtransformer further comprises a passivating layer over said top protective insulating layer.

72. The system-on-chip of claim 69, wherein said microtransformer further comprises a second layer of electrically conductive material forming at least one coil on said second layer of magnetic material.

73. The system-on-chip of claim 72 further comprising an insulating layer between said second layer of magnetic material and said second layer of electrically conductive material.

74. The system-on-chip of claim 73, wherein said microtransformer further comprises a top protective insulating layer over said second layer of electrically conductive material.

75. The system-on-chip of claim 74, wherein said microtransformer further comprises a passivating layer over said top protective insulating layer.

76. The system-on-chip of claim 64, wherein said substrate is a semiconductor substrate.

77. The system-on-chip of claim 76, wherein said semiconductor substrate is a germanium substrate.

78. The system-on-chip of claim 76, wherein said semiconductor substrate is a gallium arsenide substrate.

79. The system-on-chip of claim 64, wherein said substrate is a ceramic substrate.

80. The system-on-chip of claim 64, wherein said substrate is a quartz substrate.

81. The system-on-chip of claim 64, wherein said substrate is an Al₂O₃/TiC substrate.

82. The system-on-chip of claim 64, wherein said at least one chip contains analog circuitry.

83. The system-on-chip of claim 64, wherein said at least one chip contains digital circuitry.

84. The system-on-chip of claim 64 further comprising a power supply on said substrate.

85. The system-on-chip of claim 64 further comprising a DC-DC converter on said substrate.

86. A processor-based system, comprising:

a processor; and

an integrated circuit coupled to said processor, said integrated circuit including a through-hole microtransformer, said microtransformer being formed in a coil winding area defined by a first and second through-holes in a substrate, said coil winding area including a top surface of said substrate, a bottom surface of said substrate, and side surfaces of said through-holes, said microtransformer further comprising a first layer of magnetic material provided on said substrate in said coil winding area, a first layer of electrically conductive material forming at least one coil winding provided on said substrate in said coil winding area, and a second layer of magnetic material connected with said first layer of magnetic material.

87. The processor-based system of claim 86, wherein said microtransformer further comprises a first insulating layer formed between said substrate and said first layer of magnetic material.

88. The processor-based system of claim 87, wherein said microtransformer further comprises a second insulating layer formed between said first layer of magnetic material and said first layer of electrically conductive material.

89. The processor-based system of claim 88, wherein said microtransformer further comprises a third insulating layer between said first layer of electrically conductive material and said second layer of magnetic material.

90. The processor-based system of claim 89, wherein said microtransformer further comprises a top protective insulating layer over said second layer of magnetic material.

91. The processor-based system of claim 90, wherein said microtransformer further comprises a passivating layer over said top protective insulating layer.

92. The processor-based system of claim 89, wherein said microtransformer further comprises a second layer of electrically conductive material forming at least one coil on said second layer of magnetic material.

93. The processor-based system of claim 92 further comprising an insulating layer between said second layer of magnetic material and said second layer of electrically conductive material.

94. The processor-based system of claim 93, wherein said microtransformer further comprises a top protective insulating layer over said second layer of electrically conductive material.

95. The processor-based system of claim 94, wherein said microtransformer further comprises a passivating layer over said top protective insulating layer.

96. The processor-based system of claim 86, wherein said integrated circuit is part of a memory circuit.

97. The processor-based system of claim 86, wherein said processor and said integrated circuit are integrated on same chip.

98. The processor-based system of claim 86, wherein said substrate is a semiconductor substrate.

99. The processor-based system of claim 98, wherein said semiconductor substrate is a germanium substrate.

100. The processor-based system of claim 98, wherein said semiconductor substrate is a gallium arsenide substrate.

101. The processor-based system of claim 86, wherein said substrate is a ceramic substrate.

102. The processor-based system of claim 86, wherein said substrate is a quartz substrate.

103. The processor-based system of claim 86, wherein said substrate is an Al₂O₃/TiC substrate.