Digital analog converter and electronic device using the same
First Claim
Patent Images
1. A D/A converter circuit for converting “
- n”
bit digital data to analog signals, comprising;
a switch which is controlled by respective bits of the lower “
m”
bits of “
n”
bit digital data (“
m” and
“
n”
;
natural numbers, “
m”
<
“
n”
), and a switch which is controlled by respective bits of the upper (“
n”
−
“
m”
) bits of “
n”
bit digital data;
a capacitance, being a capacitance connected to each of said switches controlled by the respective bits of said lower “
m”
bits, which is greater by 2m−
1 times than the respective unit capacitance;
a capacitance, being a capacitance connected to each of said switches controlled by the respective bits of said upper (“
n”
−
“
m”
) bits, which is greater by 2n−
m−
1 times than the respective unit capacitance;
a coupling capacitance; and
two reset switches;
wherein two power sources and an offset power source are connected to said D/A converter circuit;
said switches select either one of the two power sources;
said two reset switches control charge of electric charges into said capacitance; and
analog signals are outputted, with the potential of said offset power source used as a reference potential, from a common connection end of a capacitance of the upper (“
n”
−
“
m”
) bits of said “
n”
bit digital video data.
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Abstract
The present invention relates to a D/A converter circuit which is capable of independently controlling the output voltage amplitude VOUT and the reference voltage. The D/A converter circuit converts “n” bit digital data (“n”: natural number) to analog signals, wherein the respective bits of said “n” bit digital data control a switch, control charge and discharge of electric charges in the capacitance connected to said switch, and output analog signals with the offset potential used as a reference potential.
-
Citations
47 Claims
-
1. A D/A converter circuit for converting “
- n”
bit digital data to analog signals, comprising;a switch which is controlled by respective bits of the lower “
m”
bits of “
n”
bit digital data (“
m” and
“
n”
;
natural numbers, “
m”
<
“
n”
), and a switch which is controlled by respective bits of the upper (“
n”
−
“
m”
) bits of “
n”
bit digital data;
a capacitance, being a capacitance connected to each of said switches controlled by the respective bits of said lower “
m”
bits, which is greater by 2m−
1 times than the respective unit capacitance;
a capacitance, being a capacitance connected to each of said switches controlled by the respective bits of said upper (“
n”
−
“
m”
) bits, which is greater by 2n−
m−
1 times than the respective unit capacitance;
a coupling capacitance; and
two reset switches;
wherein two power sources and an offset power source are connected to said D/A converter circuit;
said switches select either one of the two power sources;
said two reset switches control charge of electric charges into said capacitance; and
analog signals are outputted, with the potential of said offset power source used as a reference potential, from a common connection end of a capacitance of the upper (“
n”
−
“
m”
) bits of said “
n”
bit digital video data.
- n”
-
2. A D/A converter circuit comprising:
-
a lower bit circuit portion being a lower bit circuit portion controlled by the lower “
m”
bit (“
n” and
“
m”
;
natural numbers, “
m”
<
“
n”
) of “
n”
bit digital data, and including a switch controlled by the respective bits and a capacitance connected to said switch, which has a capacitance greater by 2m−
1 times than the unit capacitance;
an upper bit circuit portion being an upper bit circuit portion controlled by the upper (“
n”
−
“
m”
) bits of “
n”
bit digital data, and including a switch controlled by the respective bits and a capacitance connected to said switch, which has a capacitance greater by 2n−
m−
1 times than the unit capacitance;
a coupling capacitance consisting of said unit capacitance which connects said lower bit circuit portion to said upper bit circuit portion; and
two reset switches;
wherein two power sources and an offset power source are inputted therein, said two reset switches control charge of electric charges into the respective capacitances of said lower bit circuit portion and the respective capacitances of said upper bit circuit portion;
said offset power source is inputted into a common connection end of the respective capacitances of said upper bit circuit portion;
said respective switches of said lower bit circuit portion select either one of said two power sources in compliance with said bit information, and control charge and discharge of electric charges in a capacitance connected to said respective switches;
said respective switches of said upper bit circuit portion select either one of said two power sources in compliance with each bit information, and control charge and discharge of electric charges in a capacitance connected to said respective switches; and
analog signals are outputted, with the potential of said offset power source used as a reference potential, from said common connection end of said upper bit circuit portion.
-
-
3. A D/A converter circuit comprising:
-
a lower bit circuit portion being a lower bit circuit portion controlled by the lower “
m”
bit (“
n” and
“
m”
;
natural numbers, “
m”
<
“
n”
) of “
n”
bit digital data, and including a switch controlled by the respective bits and capacitance connected to said switch, which has capacitance greater by 2m−
1 times than the unit capacitance;
an upper bit circuit portion being an upper bit circuit portion controlled by the upper (“
n”
−
“
m”
) bits of “
n”
bit digital data, and including a switch controlled by the respective bits and capacitance connected to said switch, which has capacitance greater by 2n−
m−
1 times than the unit capacitance;
a coupling capacitance consisting of said unit capacitance which connects said lower bit circuit portion to said upper bit circuit portion; and
two reset switches;
wherein two power sources VH and VL and an offset power source VB are inputted therein;
said offset power source VB is inputted into a common connection end of the respective capacitances of said upper bit circuit portion; and
the output voltage VOUT outputted from said common connection end is expressed in terms of expressions (6a), (6b), (7) and (8).
-
-
4. An electronic device having an active matrix display device, said display device having a D/A converter circuit for converting “
- n”
bit digital data (“
n”
;
natural number) to analog signals;wherein respective bits of said “
n”
bit digital data control a switch and control charge and discharge of electric charges in a capacitance connected to said switch; and
analog signals are outputted with an offset voltage used as a reference potential. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
- n”
-
5. An electronic device having an active matrix display device, said display device having a D/A converter circuit for converting “
- n”
bit digital data (“
n”
;
natural number) to analog signals, which has “
n”
switches and “
n”
capacitance corresponding to the respective bits of said “
n”
bit digital data;wherein said “
n”
switches corresponding to the respective bits control charge and discharge of electric charges in said capacitances connected to each of said “
n”
switches; and
analog signals are outputted with an offset voltage used as a reference potential. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
- n”
-
6. An electronic device having an active matrix display device, said display device having a D/A converter circuit for converting “
- n”
bit digital data to analog signals, comprising;a switch which is controlled by respective bits of the lower “
m”
bits of “
n”
bit digital data (“
m” and
“
n”
;
natural numbers, “
m”
<
“
n”
), and a switch which is controlled by respective bits of the upper (“
n”
−
“
m”
) bits of “
n”
bit digital data;
a capacitance, being a capacitance connected to each of said switches controlled by the respective bits of said lower “
m”
bits, which is greater by 2m−
1 times than the respective unit capacitance;
a capacitance, being a capacitance connected to each of said switches controlled by the respective bits of said upper (“
n”
−
“
m”
) bits, which is greater by 2n−
m−
1 times than the respective unit capacitance;
a coupling capacitance; and
two reset switches;
wherein two power sources and an offset power source are connected to said D/A converter circuit;
said switches select either one of the two power sources;
said two reset switches control charge of electric charges into said capacitance; and
analog signals are outputted, with the potential of said offset power source used as a reference potential, from a common connection end of a capacitance of the upper (“
n”
−
“
m”
) bits of said “
n”
bit digital video data.- View Dependent Claims (23, 24, 25, 26, 27, 28, 29)
- n”
-
7. An electronic device having an active matrix display device, said display device having a D/A converter circuit comprising:
-
a lower bit circuit portion being a lower bit circuit portion controlled by the lower “
m”
bit (“
n” and
“
m”
;
natural numbers, “
m”
<
“
n”
) of “
n”
bit digital data, and including a switch controlled by the respective bits and a capacitance connected to said switch, which has a capacitance greater by 2m−
1 times than the unit capacitance;
an upper bit circuit portion being an upper bit circuit portion controlled by the upper (“
n”
−
“
m”
) bits of “
n”
bit digital data, and including a switch controlled by the respective bits and a capacitance connected to said switch, which has a capacitance greater by 2n−
m−
1 times than the unit capacitance;
a coupling capacitance consisting of said unit capacitance which connects said lower bit circuit portion to said upper bit circuit portion; and
two reset switches;
wherein two power sources and an offset power source are inputted therein, said two reset switches control charge of electric charges into the respective capacitances of said lower bit circuit portion and the respective capacitances of said upper bit circuit portion;
said offset power source is inputted into a common connection end of the respective capacitances of said upper bit circuit portion;
said respective switches of said lower bit circuit portion select either one of said two power sources in compliance with said bit information, and control charge and discharge of electric charges in a capacitance connected to said respective switches;
said respective switches of said upper bit circuit portion select either one of said two power sources in compliance with each bit information, and control charge and discharge of electric charges in a capacitance connected to said respective switches; and
analog signals are outputted, with the potential of said offset power source used as a reference potential, from said common connection end of said upper bit circuit portion. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36)
-
-
8. An electronic device having an active matrix display device, said display device having a D/A converter circuit comprising:
-
a lower bit circuit portion being a lower bit circuit portion controlled by the lower “
m”
bit (“
n” and
“
m”
;
natural numbers, “
m”
<
“
n”
) of “
n”
bit digital data, and including a switch controlled by the respective bits and capacitance connected to said switch, which has capacitance greater by 2m−
1 times than the unit capacitance;
an upper bit circuit portion being an upper bit circuit portion controlled by the upper (“
n”
−
“
m”
) bits of “
n”
bit digital data, and including a switch controlled by the respective bits and capacitance connected to said switch, which has capacitance greater by 2n−
m−
1 times than the unit capacitance;
a coupling capacitance consisting of said unit capacitance which connects said lower bit circuit portion to said upper bit circuit portion; and
two reset switches;
wherein two power sources VH and VL and an offset power source VB are inputted therein;
said offset power source VB is inputted into a common connection end of the respective capacitances of said upper bit circuit portion; and
the output voltage VOUT outputted from said common connection end is expressed in terms of expressions (6a), (6b), (7) and (8). - View Dependent Claims (37, 38, 39, 40, 41, 42, 43)
-
-
44. A D/A converter circuit comprising
a plurality of capacitors; -
an output terminal connected to the plurality of capacitors;
a load capacitor connected to the output terminal;
a ground potential connected to the load capacitor;
an offset power source connected to the output terminal through a reset switch;
a first voltage source and a second voltage source;
a plurality of switches connected to the plurality of capacitors, respectively, to selectively connect one of the first and second voltage sources to the corresponding capacitors.
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-
45. A display device comprising a D/A converter circuit, the D/A converter circuit comprising:
-
a plurality of capacitors;
an output terminal connected to the plurality of capacitors;
a load capacitor connected to the output terminal;
a ground potential connected to the load capacitor;
an offset power source connected to the output terminal through a reset switch;
a first voltage source and second voltage source;
a plurality of switches connected to the plurality of capacitors, respectively, to selectively connect one of the first and second voltage sources to the corresponding capacitors.
-
-
46. An electronic device comprising a D/A converter circuit comprising:
-
a plurality of capacitors;
an output terminal connected to the plurality of capacitors;
a load capacitor connected to the output terminal;
a ground potential connected to the load capacitor;
an offset power source connected to the output terminal through a reset switch;
a first voltage source and a second voltage source;
a plurality of switches connected to the plurality of capacitors, respectively, to selectively connect one of the first and the second voltage sources to the corresponding capacitors.
-
-
47. A D/A converter circuit comprising:
-
n capacitors wherein i-th capacitor has a capacitance of 2i−
1C where i is a natural number and C is a constant;
an output terminal connected to the n capacitors;
a load capacitor connected to the output terminal;
a ground potential connected to the load capacitor;
an offset power source connected to the output terminal through a reset switch;
a first voltage source and a second voltage source;
n switches connected to n capacitors, respectively, to selectively connect one of the first and the second voltage sources to the corresponding n capacitors.
-
Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
-
InventorsOsame, Mitsuaki, Nagao, Shou, Shionoiri, Yutaka, Azami, Munehiro
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Primary Examiner(s)Young, Brian
-
Application NumberUS09/449,535Time in Patent Office960 DaysField of Search341/144, 341/150, 341/143, 341/126US Class Current341/144CPC Class CodesG09G 2300/0417 Special arrangements specif...G09G 2300/0426 Layout of electrodes and co...G09G 2300/0842 forming a memory circuit, e...G09G 2310/027 Details of drivers for data...G09G 2310/0297 Special arrangements with m...G09G 2330/02 Details of power systems an...G09G 3/3233 with pixel circuitry contro...G09G 3/3275 Details of drivers for data...G09G 3/3648 using an active matrix G09G...G09G 3/3688 suitable for active matrice...H03M 1/0607 Offset or drift compensatio...H03M 1/68 with conversions of differe...H03M 1/804 with charge redistribution
