Current-driven emissive display addressing and fabrication scheme

• US 6,421,033 B1
• Filed: 03/16/2000
• Issued: 07/16/2002
• Est. Priority Date: 09/30/1999
• Status: Expired due to Fees

• Current Assignee: Teledyne Scientific & Imaging, LLC (Teledyne Technologies Incorporated)
• Original Assignee: Innovative Technology Licensing LLC
• Inventors: Zhuang, Zhiming, Winker, Bruce K., Williams, George M.
• Primary Examiner(s): Shalwala, Bipin
• Assistant Examiner(s): PIZIALI, JEFFREY J
• Application Number:
  US09/527,147
• Time in Patent Office: 852 Days
• Field of Search: 345/33, 345/36, 345/38, 345/39, 345/55, 345/87, 345/90, 345/100, 345/92, 345/98, 345/103, 315/169.3
• US Class Current: 345/55
• CPC Class Codes: G09G 2300/0465 Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
• CPC Class Codes: G09G 2300/0804 Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/0227 related to multiple interlacing, i.e. involving more fields than just one odd field and one even field
• CPC Class Codes: G09G 2310/0235 Field-sequential colour display
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays

Abstract

An addressing scheme for use with current-driven emissive displays requires that an N-row by M-column array of pixels be divided into K segments of N/K rows each. One transistor-controlled current driver is provided for each column of pixels within a segment, and all of a segment'"'"'s current drivers are connected to a respective gate address line. The array is addressed by dividing a frame time into N/K “sub-frame” times. During the first sub-frame time, the current drivers of each segment are turned on in sequence, and the first row of each segment addressed. The remaining rows are addressed in this manner during subsequent sub-frame times. The segmenting and addressing scheme reduces the duty ratio required to drive the array by a factor of K, and reduces the number of transistors required to drive the array by a factor of N/K, when compared with comparably-sized passive matrix and active matrix displays, respectively. Fabrication of the display, and other non-passive matrix displays, is simplified by placing all active components on the back side of the display panel, or on a separate printed-circuit board (PCB) which is interconnected with the pixel array via respective surface bonding pads to form a display. Fabrication is further simplified by combining the current drivers and other drive electronics into application-specific integrated circuits (ASICs).

Claims

1. A current-driven emissive display, comprising:

an array of current-driven emissive display pixels arranged into N rows and M columns, each of said pixels having a brightness which varies directly with its drive current, said array of pixels sub-divided into K segments, each of said K segments consisting of N/K rows and M columns, each of said M columns having respective column address lines,

K×

M transistor-controlled current drivers, each of said current drivers connected to a corresponding one of said column address lines, the pixels in each column of each segment connected to a respective one of said current drivers, each of said current drivers connected to drive the N/K pixels found in its respective column segment, each of said segments having a respective gate address line which is connected to each of the current drivers within the segment, each of the current drivers within a segment arranged to provide a current level to its column of pixels which corresponds to the voltage present on the current driver'"'"'s corresponding column address line when the segment'"'"'s gate address line is selected,

each of said transistor-controlled current drivers comprising;

a first transistor,

a storage device, and

a voltage-controlled current source, said first transistor connected to conduct a voltage to said storage device in response to the selection of the transistor-controlled current driver'"'"'s gate address line, said storage device storing said voltage, said voltage-controlled current source connected to provide said current level to its N/K pixels in accordance with the voltage stored on said storage device, and

a controller arranged to control said gate address lines such that each of the pixels in said array is controlled via said transistor-controlled current drivers.

2. The emissive display of claim 1, wherein each of the current drivers within a segment is arranged to provide said current level by sinking an amount of current from its column of pixels which corresponds to the voltage present on the current driver'"'"'s corresponding column address line when the segment'"'"'s gate address line is selected.

3. The emissive display of claim 1, wherein each of the current drivers within a segment is arranged to provide said current level by sourcing an amount of current to its column of pixels which corresponds to the voltage present on the current driver'"'"'s corresponding column address line when the segment'"'"'s gate address line is selected.

4. The emissive display of claim 1, wherein said controller is arranged to address each of the pixels in said array during a time T_frame, said time T_frame divided into N/K sub-frame times each having a duration T_sub given by T_frame/(N/K), said controller during a sub-frame time addressing a selected row within each segment segment-by-segment until the selected row in each of said segments has been addressed, said controller selecting and addressing a different row within each segment during each subsequent sub-frame time until each of the pixels in said array have been addressed,

said segmentation and addressing scheme reducing the duty ratio required to drive the array by a factor of K when compared with a passive matrix current-driven emissive display of the same size, and reducing the number of transistors required to drive the array by a factor of N/K when compared with an active matrix current-driven emissive display of the same size.

5. The emissive display of claim 1, wherein said current-driven emissive display pixels comprise organic emissive devices (OEDs).

6. The emissive display of claim 1, wherein each of said storage devices comprises a capacitor connected to said first transistor at a first junction, said first transistor connected to said transistor-controlled current driver'"'"'s respective gate address line and conducting a voltage from said transistor-controlled current driver'"'"'s respective column line to said capacitor when said gate address line is selected, said capacitor connected to maintain said voltage at said first junction, and

each of said voltage-controlled current sources comprises a second transistor connected to said first junction and conducting said current level between a power bus and the N/K pixels in said current driver'"'"'s column segment in accordance with the voltage at said first junction.

7. The emissive display of claim 1, wherein said display comprises a display panel which contains said array of current-driven emissive display pixels and a printed circuit board (PCB) which contains said K×

M transistor-controlled current drivers, said PCB interconnected to said display panel to form said current-driven emissive display.

8. The emissive display of claim 7, wherein said transistor-controlled current drivers are contained within one or more application-specific integrated circuits (ASICs).

9. The emissive display of claim 7, wherein said display panel includes surface bonding pads by which said pixels can be driven which are accessible from the back side of the display panel and said PCB includes a plurality of surface bonding pads on the side of said PCB opposite said transistor-controlled current drivers, said PCB and said display panel brought together such that their respective surface bonding pads contact each other to effect the interconnections necessary to form said current-driven emissive display.

10. The emissive display of claim 9, wherein said display panel further comprises a patterned insulator layer over said display panel'"'"'s surface bonding pads, said insulator layer patterned to electrically isolate said display panel'"'"'s surface bonding pads from each other and to provide openings above each of said display panel'"'"'s surface bonding pads which enable the corresponding bonding pads of said display panel and said PCB to make electrical contact with each other.

11. The emissive display of claim 10, further comprising a conductive adhesive applied in each of said openings to bind said display panel to said PCB and to ensure that a conductive path exists between each PCB surface bonding pad and its corresponding display panel surface bonding pad.

12. The emissive display of claim 9, wherein said PCB and said display panel are brought together using roll-to-roll lamination.

13. The emissive display of claim 9, wherein said PCB and said display panel are fabricated on flexible substrates.

14. The emissive display of claim 1, wherein said display comprises a display panel having said pixel array fabricated on one side and said K×

M transistor-controlled current drivers mounted on the side of said display panel opposite said pixel array, said current drivers interconnected to said pixel array to form said current-driven emissive display.

15. The emissive display of claim 14, wherein said display comprises:

a substrate, said K×

M transistor-controlled current drivers mounted on one side of said substrate,

a first set of electrodes on said substrate, said first set of electrodes connected to said K×

M transistor-controlled current drivers through said substrate,

a second set of electrodes,

a material disposed between said first and second sets of electrodes which with said electrodes forms pixels, said material when driven with a current emitting light, and

a substantially transparent protective layer on said pixels, light produced by said pixels emitted from said display through said protective layer.

16. The emissive display of claim 15 wherein said substrate and said protective layer hermetically seal the display from moisture and oxygen.

17. The emissive display of claim 1, wherein said array has N/K row address lines, each of which is connected to a corresponding row of pixels in each of said segments, the pixels in each column of each segment connected between a row address line and a respective one of said current drivers.

18. The emissive display of claim 17, wherein said controller is arranged to address each of the pixels in said array during a time T_frame, said time T_frame divided into N/K sub-frame times each having a duration T_sub given by T_frame/(N/K), said controller during a sub-frame time addressing a selected row within each segment segment-by-segment until the selected row in each of said segments has been addressed, said controller selecting and addressing a different row within each segment during each subsequent sub-frame time until each of the pixels in said array have been addressed, said controller arranged to select each of said gate address lines in sequence at the start of each of said sub-frame times, the duration T_gate for which each of said gate address lines is selected being much less than T_sub/K such that each of said current drivers provides its programmed current level for nearly all of a sub-frame time.

19. The emissive display of claim 1, wherein said array has N row address lines, each of which is connected to a respective one of said rows of pixels, the pixels in each column of each segment connected between the pixel'"'"'s row address line and a respective one of said current drivers.

20. The emissive display of claim 19, wherein said controller is arranged to address each of the pixels in said array during a time T_frame, said time T_frame divided into N/K sub-frame times each having a duration T_sub given by T_frame/(N/K), said controller during a sub-frame time addressing a given row within each segment segment-by-segment until the given row in each of said segments has been addressed, said given rows addressed by selecting their respective row address lines, the selection of the given rows'"'"' row address lines being staggered evenly throughout said sub-frame time, each of the given rows'"'"' row address lines being selected for a time equal to a sub-frame time T_sub, said controller selecting and addressing a different row within each segment during each subsequent sub-frame time until each of the pixels in said array have been addressed, said controller arranged to select each of said gate address lines in sequence during each of said sub-frame times, the duration T_gate for which each of said gate address lines is selected being equal to T_sub/K.