Array board interconnect system and method

• US 6,421,251 B1
• Filed: 02/05/1998
• Issued: 07/16/2002
• Est. Priority Date: 05/02/1997
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Axis Systems Incorporated (Cadence Systems, Inc.)
• Inventors: Lin, Sharon Sheau-Pyng
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Knox, Lonnie A
• Application Number:
  US09/019,383
• Time in Patent Office: 1,622 Days
• Field of Search: 395/500.17, 395/500.18, 395/500.44, 361/686, 361/785, 361/795, 361/788, 361/803, 174/264, 326/103, 257/713, 257/724, 703/27, 703/20, 703/24
• US Class Current: 361/788
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

The FPGA array in the Simulation system is provided on the motherboard through a particular board interconnect structure to provide easy expandability and maximize packaging density with a single PCB design. Each chip may have up to eight sets of interconnections, where the interconnections are arranged according to adjacent direct-neighbor interconnects (i.e., N[73:0], S[73:0], W[73:0], E[73:0]), and one-hope neighbor interconnects (i.e., NH[27:0], SH[27:0], XH[36:0], XH[72:37]), excluding the local bus connections, within a single board and across different boards. Each chip is capable of being interconnected directly to adjacent neighbor chips, or in one hop to a non-adjacent chip located above, below, left, and right. In the X direction (east-west), the array is connected in a torus. In the Y direction (north-south), the array is connected in a column. The interconnects alone can couple logic devices and other components within a single board. However, the inter-board connectors are provided to couple these boards and interconnects together across different boards to carry signals between (1) the PCI bus via the motherboard and the array boards, and (2) any two array boards, all without passing through a backplane or motherboard to achieve the highest packaging density. A motherboard connector connects the board to the motherboard, and hence, to the PCI bus, power, and ground. For some boards, the motherboard connector is not used for direct connection to the motherboard. In a six-board configuration, only boards 1, 3 and 5 are directly connected to the motherboard while the remaining boards 2, 4, and 6 rely on their neighbor boards for motherboard connectivity. Thus, every other board is directly connected to the motherboard, and interconnects and local buses of these boards are coupled together via inter-board connectors arranged solder-side to component-side. PCI signals are routed through one of the boards (typically the first board) only. Power and ground are applied to the other motherboard connectors for those boards. Placed solder-side to component-side, the various inter-board connectors allow communication among the PCI bus components, the FPGA logic devices, memory devices, and various Simulation system control circuits.

Claims

1. A multi-board interconnect system in a motherboard for an electronic system, the motherboard containing a motherboard connector and a host computer system, the host computer including a processor, a main memory, a processor bus system coupled to the processor and main memory, and a system bus coupled to the processor bus, comprising:

a local bus interconnect separated from the motherboard connector and coupled to the system bus;

a first board directly coupled to the motherboard via the motherboard connector and the local bus interconnect, and including a plurality of first hardware elements and a first logic bus coupling the plurality of first hardware elements and the first logic bus coupled to the local bus interconnect; and

a second board directly coupled to the first board via the local bus interconnect and including a plurality of second hardware elements and a second logic bus coupling the plurality of second hardware elements and the second logic bus coupled to the local bus interconnect, wherein at least one of the plurality of first hardware elements in the first board is coupled to at least one of the plurality of second hardware elements in the second board via the local bus.

2. The system of claim 1, wherein the plurality of first hardware elements is a first logic device and a first memory device.

3. The system of claim 2, wherein the plurality of second hardware elements is a second logic device and a second memory device.

4. The system of claim 3, wherein the first board and the second board are coupled together through a first inter-board connector which is separated from the motherboard connector and couples the first logic device and the second logic device.

5. The system of claim 4, further comprising:

a local bus controller coupled to the system bus and the local bus interconnect on the first board for controlling data transfer between the system bus and the local bus.

6. The system of claim 5, further comprising:

a logic bus controller coupled to the local bus interconnect and the first logic bus on the first board, and coupled to the local bus interconnect and the second logic bus on the second board, for controlling data transfer among the local bus interconnect, the first logic bus, and the second logic bus.

7. The system of claim 1, wherein the first board has a first solder side and a first component side, and the second board has a second solder side and a second component side, and the local bus interconnect couples the first component side and the second solder side.

8. The system of claim 4, wherein the first board has a first solder side and a first component side, and the second board has a second solder side and a second component side, and the first inter-board connector couples the first component side to the second solder side.

9. The system of claim 4, further comprising:

a third board directly coupled to the motherboard and the local bus interconnect, the third board having a third component side and a third solder side, the local bus interconnect coupling the third board and the second board.

10. The system of claim 9 further comprising:

a second inter-board connector which is separated from the motherboard connector and connects the second board and the third board, wherein the second inter-board connector couples the second component side to the third solder side.

11. An interconnect layout system for connecting a plurality of boards to a motherboard and to each other, where the motherboard contains a motherboard connector, comprising:

at least one board and each board is designated board n, where n is a positive integer from 1 to N, and N represents a maximum number of desired boards;

at least one logic device and each logic device is designated logic device m(n), where m is a positive integer from 1 to M, and M represents a maximum number of desired logic devices in a column on the board n;

at least one horizontal connection and each horizontal connection is designated horizontal connection j(n), where j is a positive integer from 1 to J, and J represents a maximum number of desired horizontal connections, and the horizontal connections couple the logic devices in board n; and

at least one vertical interconnect and each vertical interconnect is designated vertical interconnect k, where k is a positive integer from 1 to K, and K represents a maximum number of desired vertical interconnects on the board n, and the vertical interconnect k couples the logic devices in adjacent board n and board n+1 and is spacially separated from the motherboard connector.

12. The system of claim 11, wherein the logic devices in the same board are coupled to each other via the horizontal connection j(n).

13. The system of claim 12, wherein a logic device in board n is coupled to another logic device in board N+1 directly via the vertical interconnect k.

14. The system of claim 12, wherein a logic device in board n is coupled to another logic device in board N+1 in one hop via the vertical interconnect k.

15. The system of claim 11, wherein the vertical interconnect k further comprises:

at least one direct interconnect connecting a logic device m in board n and logic device m+1 in board n, where m+1 is not greater than M.

16. The system of claim 11, wherein the vertical interconnect k further comprises:

at least one one-hop interconnect connecting a logic device m in board n and logic device m+2 in board n, where m+1 is not greater than M.

17. The system of claim 11, wherein the vertical interconnect k further comprises:

at least one direct interconnect connecting a logic device m in board n and logic device m in board n+1, where n+1 is not greater than N.

18. The system of claim 11, wherein the vertical interconnect k further comprises:

at least one one-hop interconnect connecting logic device m in board n and logic device m in board n+2, where n+2 is not greater than N.

19. The system of claim 11, wherein the vertical interconnect k further comprises:

at least one one-hop interconnect connecting a logic device m in board n and logic device m+1 in board n+1, where m+1 is not greater than M and n+1 is not greater than N.

20. A multi-board connection system in a motherboard for an electronic system, the motherboard containing a motherboard connector and a host computer system, the host computer including a processor, a main memory, a processor bus system coupled to the processor and main memory, and a system bus coupled to the processor bus, comprising:

an inter-board connection separated from the motherboard connector;

a first board directly coupled to the motherboard via the motherboard connector and including a plurality of first hardware elements and a first logic bus coupling the plurality of first hardware elements;

a second board directly coupled to the first board via the inter-board connection and including a plurality of second hardware elements and a second logic bus coupling the plurality of second hardware elements, wherein at least one of the plurality of first hardware elements in the first board is coupled to at least one of the plurality of second hardware elements in the second board via the inter-board connection; and

a third board directly coupled to the second board via the inter-board connection and directly coupled to the motherboard via the motherboard connector, and the third board including a plurality of third hardware elements wherein at least one of the plurality of second hardware elements in the second board is coupled to at least one of the plurality of third hardware elements in the third board via the inter-board connection.

21. The system of claim 20, wherein the plurality of first hardware elements is a first logic device and a first memory device.

22. The system of claim 21, wherein the plurality of second hardware elements is a second logic device and a second memory device.

23. The system of claim 22, wherein the first board and the second board are coupled together through a first inter-board connector which is separated from the motherboard connector and couples the first logic device and the second logic device.

24. The system of claim 23, further comprising:

a local bus in the first board and the second board coupled to the system bus; and

a local bus controller coupled to the system bus and the local bus on the first board for controlling data transfer between the system bus and the local bus.

25. The system of claim 24, further comprising:

a logic bus controller coupled to the local bus and the first logic bus on the first board, and coupled to the local bus and the second logic bus on the second board, for controlling data transfer among the local bus, the first logic bus, and the second logic bus.

26. The system of claim 20, wherein the first board has a first solder side and a first component side, and the second board has a second solder side and a second component side, and the inter-board connection couples the first component side and the second solder side.

27. The system of claim 23, wherein the first board has a first solder side and a first component side, and the second board has a second solder side and a second component side, and the first inter-board connector couples the first component side to the second solder side.

28. The system of claim 23, further comprising:

a third board directly coupled to the motherboard via the motherboard connection and the inter-board connection coupling the third board and the second board.

29. The system of claim 28, wherein the third board having a third component side and a third solder side, the system further comprising:

a second inter-board connector which is separated from the motherboard connector and connects the second board and the third board, wherein the second inter-board connector couples the second component side to the third solder side.

30. The system of claim 20, wherein the plurality of first hardware elements in the first board are arranged in a two-dimensional matrix of rows and columns.

31. The system of claim 30, wherein the plurality of second hardware elements in the second board are arranged in a two-dimensional matrix of rows and columns.

32. The system of claim 30, wherein the first board is expandable to include additional rows of first hardware elements.

33. A multi-board connection system in a mother board for an electronic system, the motherboard containing a motherboard connector and a host computer system, the host computer including a processor, a main memory, a processor bus system coupled to the processor and main memory, and a system bus coupled to the processor bus, comprising:

an inter-board connection separated from the motherboard connector;

a first board directly coupled to the motherboard via the motherboard connector and including a plurality of first hardware elements and a first logic bus coupling the plurality of first hardware elements;

a second board directly coupled to the first board via the inter-board connection and including a plurality of second hardware elements and a second logic bus coupling the plurality of second hardware elements, wherein at least one of the plurality of first hardware elements in the first board is coupled to at least one of the plurality of second hardware elements in the second board via the inter-board connection; and

a third board directly coupled to the second board via the inter-board connection and directly coupled to the motherboard via the motherboard connector, and the third board including a plurality of third hardware elements, wherein at least one of the plurality of first hardware elements in the first board is coupled to at least one of the plurality of third hardware elements in the third board via the inter-board connection.