Method for controlling experimental inventory

• US 6,421,287 B1
• Filed: 05/09/2000
• Issued: 07/16/2002
• Est. Priority Date: 12/04/1997
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Jacobs, Marc A.
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/506,673
• Time in Patent Office: 798 Days
• Field of Search: 365/201, 365/200, 365/185.09, 324/765, 324/769
• US Class Current: 365/201
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: H01L 2223/5444 for electrical read out

Abstract

A method is provided for programming and reading manufacturing information upon non-volatile storage elements of the integrated circuit. The manufacturing information includes the particular processing recipe and layout of the integrated circuit, each recipe or layout indicative of a specific hardware revision. The storage elements may be programmed prior to assembling the integrated circuit within a semiconductor package, and the programmed elements are read prior to shipping the packaged integrated circuit to a customer. If the read hardware revision is not qualified for release, the product will be placed in a staging area and prevented from shipping to a customer or end user. Thus, the programmed hardware revision serves to gate product at test before shipping that product to a customer. The manufacturing information is programmed by the manufacturer and is inaccessible by a customer since the address space which contains product engineering bits is known only to the manufacturer.

Claims

1. A method for determining if an integrated circuit is suitable for shipment, comprising:

writing electronic indicia into storage locations on the integrated circuit, wherein the indicia correspond to manufacturing parameters for producing the integrated circuit; and

during testing of the integrated circuit, reading the written indicia to determine shipment suitability of the integrated circuit.

2. The method as recited in claim 1, wherein said writing comprises:

addressing at least one of the storage locations; and

providing one or more bits to the addressed storage locations for identifying a wafer fabrication processing sequence.

3. The method as recited in claim 1, wherein said writing comprises:

addressing at least one of the storage locations; and

providing one or more bits to the addressed storage locations for identifying equipment used to fabricate the integrated circuit.

4. The method as recited in claim 1, wherein said writing comprises:

addressing at least one of the storage location; and

providing one or more bits to the addressed storage locations for identifying one or more layout revisions corresponding to one or more masks for patterning the integrated circuit.

5. The method as recited in claim 1, wherein an indication of shipment suitability given by the written indicia is independent of a performance of the integrated circuit in testing.

6. The method as recited in claim 1, wherein said writing comprises writing electronic indicia into storage locations which are inaccessible during normal operation of the integrated circuit.

7. The method as recited in claim 1, wherein said writing is performed prior to assembly of the integrated circuit into a package.

8. A method for determining whether an integrated circuit is suitable for shipment, said method comprising:

writing electronic indicia into storage locations on the integrated circuit, wherein the indicia characterize a suitability of the integrated circuit for shipment; and

subsequently reading the written indicia to determine shipment suitability of the integrated circuit.

9. The method as recited in claim 8, wherein said writing comprises writing electronic indicia identifying a hardware revision specific to the integrated circuit.

10. The method as recited in claim 8, wherein said hardware revision comprises a revision to a processing recipe, processing tool or layout specific to the integrated circuit.

11. The method as recited in claim 8, wherein said writing comprises writing electronic indicia identifying a software revision specific to the integrated circuit.

12. The method as recited in claim 8, wherein said software revision comprises a particular version of software used to program memory elements of the integrated circuit.

13. The method as recited in claim 8, wherein the suitability of the integrated circuit for shipment characterized by the written indicia is independent of a performance of the integrated circuit in testing.

14. The method as recited in claim 8, wherein said writing comprises writing electronic indicia into storage locations which are inaccessible during normal operation of the integrated circuit.

15. The method as recited in claim 8, wherein said writing is performed prior to assembly of the integrated circuit into a package.

16. A method of determining whether an integrated circuit is suitable for shipment, said method comprising reading electronic indicia which characterize a suitability of the integrated circuit for shipment from storage locations on the integrated circuit to determine shipment suitability of the integrated circuit.

17. The method as recited in claim 16, wherein the suitability of the integrated circuit for shipment indicated by the electronic indicia is independent of a performance of the integrated circuit in testing.

18. The method as recited in claim 16, wherein said reading comprises reading from storage locations which are inaccessible during normal operation of the integrated circuit.

19. The method as recited in claim 16, wherein said reading comprises reading electronic indicia identifying a hardware revision specific to the integrated circuit.

20. The method as recited in claim 16, wherein said reading comprises reading electronic indicia identifying a software revision specific to the integrated circuit.