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High speed packet switching controller for telephone switching system

  • US 6,421,341 B1
  • Filed: 10/15/1998
  • Issued: 07/16/2002
  • Est. Priority Date: 10/16/1997
  • Status: Expired due to Term
First Claim
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1. A high speed packet switching controller comprising:

  • a row address decoder for decoding a weight row address which is inputted thereto;

    a column address decoder for decoding a weight column address which is inputted thereto;

    a matrix array for outputting varied voltage in accordance with an external weight value in accordance with weight row address and column address signals;

    a neural network for producing a final crossbar switching control signal; and

    a internal neural data bus for transmitting said weight row address and column address signals;

    wherein said neural network comprises;

    a matrix ring part for varying output voltage in accordance with an input weight value; and

    at least a non-linear amplifier for amplifying an output signal of said matrix ring part.

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