Method and circuit for analysis of the operation of a microcontroller using signature analysis of data and instructions

• US 6,421,790 B1
• Filed: 05/10/1999
• Issued: 07/16/2002
• Est. Priority Date: 05/10/1999
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Delphi Technologies, Inc. (BorgWarner Incorporated)
• Inventors: Fruehling, Terry L., Spall, James M., Helm, Troy L.
• Primary Examiner(s): Iqbal, Nadeem
• Application Number:
  US09/309,135
• Time in Patent Office: 1,163 Days
• Field of Search: 714/30, 714/31, 714/32, 714/34, 714/36, 714/39, 714/43, 714/48, 714/25, 714/27, 714/12
• US Class Current: 714/30
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 11/27 Built-in tests

Abstract

A method and circuit for determining the health of a microcontroller is a bus having a data line and instruction line. A first CPU is coupled to the bus. A reference memory stores a reference signature. A shift register is coupled to the bus and generates a second signature in response to the data line and instruction line. A controller is coupled to the register and the reference memory for controlling reading of the data line and instruction line. The controller compares the reference signature to the second signature. The controller generates a fault signal when the reference signature is unequal to the second signature.

Claims

1. A circuit comprising:

a bus having a data line and instruction line;

a firs t CPU coupled to the bus;

a reference memory storing a reference signature;

a shift register coupled to the bus, generating a second signature in response to said data line and instruction line; and

a controller coupled to the register and said reference memory for controlling reading of said data line and instruction line, said controller being adapted to disable at least one interrupt source and enable a signature ready interrupt, to execute an interrupt service routine to obtain the second signature, compare said reference signature to said second signature, and to generate a fault signal when the reference signature is unequal to the second signature.

2. A circuit as recited in claim 1 further comprising a total cycle counter coupled to the controller.

3. A circuit as recited in claim 1 wherein said shift register comprises a linear feedback shift register.

4. A circuit as recited in claim 1 wherein said first register is comprised of a first data register coupled to said bus, and a control register coupled to said bus.

5. A circuit as recited in claim 1 further comprising a second data register coupled to said bus.

6. A circuit as recited in claim 1 further comprising a plurality of feedback register stages coupled to said first register, said second register and said control register.

7. A circuit as recited in claim 1 further comprising a second CPU coupled to the bus.

8. A circuit as recited in claim 1 further comprising an isolation gate coupled to said bus between said first CPU and said second CPU.

9. A standalone self test module comprising:

a bus having a control line having instructions thereon, and a data bus having data thereon;

a linear feedback shift register coupled to said bus, said linear feedback shift register generating a signature in response to said instructions and said data;

a bus control logic circuit coupled to the control and coupled to the shift register for controlling reading of said data and instruction, said control logic circuit being adapted to disable at least one interrupt source and enable a signature ready interrupt, to execute an interrupt service routine to obtain a second signature and compare said reference signature and said second signature, and to generate a fault signal when the reference signature is unequal to the second signature.

10. A circuit as recited in claim 9 further comprising a total cycle counter coupled to the bus control logic.

11. A circuit as recited in claim 9 wherein said register is comprised of a first data register coupled to said bus, and control register coupled to said bus.

12. A circuit as recited in claim 9 further comprising a second data register coupled to said bus.

13. A circuit as recited in claim 9 further comprising a plurality of feedback register stages coupled to said first register, said second register and said control register.

14. A circuit as recited in claim 9 further comprising an isolation gate coupled to said bus between said first CPU and said second CPU.

15. A method of validating the operation of a microcontroller unit during initialization, said method comprising the steps of:

storing a reference signature in a memory;

retrieving the reference signature from memory;

executing a pre-initialization routine;

disabling all interrupt sources;

enabling a signature ready interrupt;

executing an interrupt service routine to obtain a second signature;

comparing the reference signature to the second signature to obtain a comparison; and

,

indicating a fault in response to the comparison.

16. A method as recited in claim 15 wherein the step of executing an interrupt service routine comprises the step of obtaining a pre-initialization signature through a linear feedback shift register.

17. A method as recited in claim 15 wherein the steps of obtaining a pre-initialization signature comprises the steps of non-intrusively accumulating data and instructions to a linear feedback shift register.

18. A method as recited in claim 15 wherein the step of comparing comprises the step of comparing the reference signature to the pre-initialization signature.

19. A method as recited in claim 15 wherein the step of wherein the step of retrieving the reference signature from memory comprises the step of retrieving the reference signature from a memory block adjacent to the tested memory block.

20. A method as recited in claim 15 wherein the step of wherein the steps of occur in a foreground mode.