System and method of computation in a programmable logic device using virtual instructions
First Claim
1. A method for computation in a programmable logic device (PLD), the PLD including a logic plane and a plurality of memory planes, the method comprising:
- determining a first instruction of a computation task, wherein the first instruction has a first input pattern and a first output pattern;
determining a second instruction of the computation, wherein the second instruction has a second input pattern and a second output pattern, further wherein the second instruction receives data from the first instruction; and
comparing the first output pattern to the second input pattern, wherein if the first output pattern fails to match the second input pattern, then inserting a pattern manipulation instruction, and wherein if the first output pattern matches the second input pattern, then completing the computation task.
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Abstract
An FPGA configuration provides a virtual instruction. In a generic computation, the output pattern of a first instruction is compared to the input pattern of a second instruction. If the input and output patterns of the first and second instructions do not match, then a pattern manipulation instruction is inserted between the first and second instructions. At this point, the input and output patterns of the first and second instructions should match and the computation task can be completed. The method of providing virtual instructions is applicable to any FPGA. In a standard FPGA, the data stored in the storage elements of the FPGA, such as flip-flops, is retained for the next configuration of the FPGA. In this manner, successive configurations can communicate data using the patterns of the storage elements, thereby allowing standard FPGAs to implement virtual instructions. Alternatively, a standard FPGA could write out data to an external memory using a predetermined pattern of addresses. In a subsequent configuration of the FPGA, the device could read data back from this pattern of addresses in the external memory. This embodiment allows various patterns of addresses, corresponding to data, to be used in any appropriate subsequent configuration of the FPGA. In this manner, the plurality of memory planes, previously provided on the dynamically reconfigurable FPGA, can be implemented off-chip.
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Citations
23 Claims
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1. A method for computation in a programmable logic device (PLD), the PLD including a logic plane and a plurality of memory planes, the method comprising:
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determining a first instruction of a computation task, wherein the first instruction has a first input pattern and a first output pattern;
determining a second instruction of the computation, wherein the second instruction has a second input pattern and a second output pattern, further wherein the second instruction receives data from the first instruction; and
comparing the first output pattern to the second input pattern, wherein if the first output pattern fails to match the second input pattern, then inserting a pattern manipulation instruction, and wherein if the first output pattern matches the second input pattern, then completing the computation task. - View Dependent Claims (2, 3, 4, 5)
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6. A method for computation in a programmable logic device (PLD), the PLD including a logic plane and at least one memory plane, the method comprising:
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providing a first virtual instruction corresponding to a first configuration of the logic plane;
providing a second virtual instruction corresponding to a second configuration of the logic plane;
wherein the first virtual instruction provides a predetermined data pattern on the memory plane to the second virtual instruction. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A computation system for a programmable logic device, the system comprising:
a virtual instruction library, wherein each virtual instruction operates on user data in the programmable logic device, wherein the virtual instruction library includes a plurality of templates. - View Dependent Claims (19, 20, 21, 22, 23)
Specification