Flash memory with ultra thin vertical body transistors

• US 6,424,001 B1
• Filed: 02/09/2001
• Issued: 07/23/2002
• Est. Priority Date: 02/09/2001
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): Weiss, Howard
• Application Number:
  US09/780,169
• Publication Number:
  US 20020109163A1
• Time in Patent Office: 529 Days
• Field of Search: 257/315, 257/353
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Structures and method for Flash memory with ultra thin vertical body transistors are provided. The Flash memory includes an array of memory cells including floating gate transistors. Each floating gate transistor includes a pillar extending outwardly from a semiconductor substrate. The pillar includes a single crystalline first contact layer and a second contact layer vertically separated by an oxide layer. A single crystalline vertical transistor is formed along side of the pillar. The single crystalline vertical transistor includes an ultra thin single crystalline vertical body region which separates an ultra thin single crystalline vertical first source/drain region and an ultra thin single crystalline vertical second source/drain region. A floating gate opposes the ultra thin single crystalline vertical body region, and a control gate separated from the floating gate by an insulator layer.

Claims

1. A floating gate transistor, comprising:

a pillar extending outwardly from a semiconductor substrate, wherein the pillar includes a single crystalline first contact layer and a second contact layer vertically separated by an oxide layer;

a single crystalline vertical transistor is formed along side of the pillar, wherein the single crystalline vertical transistor includes an ultra thin single crystalline vertical body region which separates an ultra thin single crystalline vertical first source/drain region and an ultra thin single crystalline vertical second source/drain region;

a floating gate opposing the ultra thin single crystalline vertical body region; and

a control gate separated from the floating gate by an insulator layer.

2. The floating gate transistor of claim 1, wherein the ultra thin single crystalline vertical body region includes a channel having a vertical length of less than 100 nanometers.

3. The floating gate transistor of claim 1, wherein the ultra thin single crystalline vertical body region has a horizontal width of less than 10 nanometers.

4. The floating gate transistor of claim 1, wherein the ultra thin single crystalline vertical body region is formed from solid phase epitaxial growth.

5. A memory cell, comprising:

a pillar extending outwardly from a semiconductor substrate, wherein the pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;

a single crystalline vertical transistor formed along side of the pillar, wherein the single crystalline vertical transistor includes;

an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;

an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;

an ultra thin single crystalline vertical body region formed along side of the oxide layer, wherein the single crystalline vertical body region couples the first source/drain region to the second source/drain region; and

a floating gate opposing the vertical body region and separated therefrom by a gate oxide;

a control gate separated from the floating gate by an insulator layer;

a buried bit line formed of single crystalline semiconductor material and disposed below the ultra thin single crystalline vertical body region, wherein the buried bit line is coupled to the first contact layer; and

a data line coupled to the second contact layer.

6. The memory cell of claim 5, wherein the buried bit line is more heavily doped than the first contact layer and is formed integrally with the first contact layer.

7. The memory cell of claim 5, wherein the ultra thin single crystalline vertical body region includes a p-type channel having a vertical length of less than 100 nanometers.

8. The memory cell of claim 7, wherein the ultra thin single crystalline vertical body region has a horizontal width of less than 10 nanometers.

9. The memory cell of claim 5, wherein the pillar extends outwardly from an insulating portion of the semiconductor substrate.

10. The memory cell of claim 5, wherein the semiconductor substrate includes a silicon on insulator substrate.

11. A memory cell, comprising:

a pillar extending outwardly from a semiconductor substrate, wherein the pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;

a single crystalline vertical transistor formed along side of the pillar, wherein the single crystalline vertical transistor includes;

an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;

an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;

an ultra thin single crystalline vertical body region formed along side of the oxide layer, wherein the single crystalline vertical body region couples the first source/drain region to the second source/drain region; and

a floating gate opposing the vertical body region and separated therefrom by a gate oxide;

a control gate separated from the floating gate by an insulator layer;

a buried bit line formed of single crystalline semiconductor material and disposed below the ultra thin single crystalline vertical body region, wherein the buried bit line is coupled to the first contact layer;

a data line coupled to the second contact layer; and

wherein the floating gate is formed in a trench below a top surface of the pillar for addressing the ultra thin single crystalline vertical body region.

12. The memory cell of claim 11, wherein the control gate is formed in the trench below the top surface of the pillar.

13. The memory cell of claim 11, wherein the floating gate includes a horizontally oriented floating gate, wherein a vertical side of the horizontally oriented floating gate has a length of less than 100 nanometers.

14. The memory cell of claim 11, wherein the floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

15. A flash memory cell, comprising:

a pillar extending outwardly from a semiconductor substrate, wherein the pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;

a pair of single crystalline vertical transistors formed along opposing sides of the pillar, wherein each single crystalline vertical transistor includes;

an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;

an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;

an ultra thin single crystalline vertical body region formed along side of the oxide layer, wherein the single crystalline vertical body region couples the first source/drain region to the second source/drain region;

a floating gate opposing the vertical body region and separated therefrom by a gate oxide;

wherein a horizontal junction depth for the first and the second ultra thin single crystalline vertical source/drain regions is much less than a vertical length of the ultra thin single crystalline vertical body region;

a control gate separated from the floating gate by an insulator layer;

a buried bit line formed of single crystalline semiconductor material and disposed below the single crystalline vertical body regions, wherein the buried bit line is coupled to the first contact layer; and

a data line coupled to the second contact layer.

16. The flash memory cell of claim 15, wherein each floating gate is independently disposed in a pair of trenches on opposing sides of the pillar such that each floating gate is below a top surface of the pillar.

17. The flash memory cell of claim 16, wherein the control gate is formed in the trench below the top surface of the pillar.

18. The flash memory cell of claim 15, wherein each ultra thin single crystalline vertical body region includes a p-type channel having a vertical length of less than 100 nanometers.

19. The flash memory cell of claim 15, wherein the buried bit line is formed integrally with the first contact layer and is separated from the semiconductor substrate by an oxide layer.

20. The flash memory cell of claim 15, wherein each floating gate includes a horizontally oriented floating gate having a vertical side length of less than 100 nanometers.

21. The flash memory cell of claim 15, wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

22. An array of memory cells, comprising:

a number of pillars extending outwardly from a semiconductor substrate, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;

a number of single crystalline vertical transistors formed along selected sides of the pillars, wherein each single crystalline vertical transistor includes;

an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;

an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;

an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions; and

a floating gate opposing the vertical body region and separated therefrom by a gate oxide;

a plurality of buried bit lines formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells; and

a plurality of control lines separated from each floating gate by an insulator layer.

23. The array of memory cells of claim 22, wherein each floating gate is formed in a trench below a top surface of each pillar.

24. The array of memory cells of claim 23, wherein each floating gate includes a horizontally oriented floating gate having a vertical side of less than 100 nanometers, and wherein the horizontally oriented floating gate are separated by a floating gate oxide from the ultra thin single crystalline vertical body regions on opposing sides of the trench for column adjacent pillars.

25. The array of memory cells of claim 24, wherein the plurality of control lines are disposed vertically above the floating gates.

26. The array of memory cells of claim 22, wherein each single crystalline vertical body region includes a p-type channel having a vertical length of less than 100 nanometers.

27. The array of memory cells of claim 22, wherein each of the plurality of buried bit lines is separated by an oxide layer from the semiconductor substrate.

28. The array of memory cells of claim 22, wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

29. An array of flash memory cells, comprising:

a number of pillars extending outwardly from a semiconductor substrate, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;

a pair of single crystalline vertical transistors formed along opposing sides of each pillar, wherein each single crystalline vertical transistor includes;

an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;

an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;

an ultra thin single crystalline vertical body region formed along side of the oxide layer and which couples the first and the second source/drain regions; and

a floating gate opposing the vertical body region and separated therefrom by a floating gate oxide;

a plurality of buried bit lines formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells;

a plurality of control lines separated from each floating gate by an insulator layer; and

a plurality of data lines coupled to the second contact layer in row adjacent pillars.

30. The array of flash memory cells of claim 29, wherein each floating gate is formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the ultra thin single crystalline vertical body regions in column adjacent pillars on opposing sides of the trench, and wherein the pair of floating gates are separated by an insulator layer.

31. The array of flash memory cells of claim 30, wherein the plurality of control lines are formed in the trench below the top surface of the pillar and between the pair of floating gates, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

32. The array of flash memory cells of claim 30, wherein the plurality of control lines are disposed vertically above the floating gates.

33. The array of flash memory cells of claim 29, wherein each floating gate includes a horizontally oriented floating gate having a vertical side of less than 100 nanometers, and wherein the horizontally oriented floating gate is separated by a floating gate oxide from the ultra thin single crystalline vertical body regions on opposing sides of the trench for column adjacent pillars.

34. The array of flash memory cells of claim 29, wherein the plurality of control lines are disposed vertically above the floating gates.

35. The array of flash memory cells of claim 29, wherein each single crystalline vertical transistor has a vertical length of less than 100 nanometers and a horizontal width of less than 10 nanometers.

36. An electronic system, comprising:

a processor; and

a memory device coupled to the processor, wherein the memory device includes a memory cell array, and wherein each memory cell in the memory array includes;

a pillar extending outwardly from a semiconductor substrate, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;

a single crystalline vertical transistor formed along selected sides of each pillars, wherein each single crystalline vertical transistor includes;

an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;

an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;

an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions; and

a floating gate opposing the vertical body region and separated therefrom by a gate oxide;

a plurality of buried bit lines formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells; and

a plurality of control lines separated from each floating gate by an insulator layer.

37. The electronic system of claim 36, wherein each floating gate is formed in a trench below a top surface of each pillar.

38. The electronic system of claim 36, wherein each floating gate includes a horizontally oriented floating gate having a vertical side of less than 100 nanometers, and wherein the horizontally oriented floating gates are separated by a floating gate oxide from the ultra thin single crystalline vertical body regions on opposing sides of the trench for column adjacent pillars.

39. The electronic system of claim 36, wherein the plurality of control lines are disposed vertically above the floating gates.

40. The electronic system of claim 36, wherein each single crystalline vertical body region includes a p-type channel having a vertical length of less than 100 nanometers.

41. The electronic system of claim 36, wherein each of the plurality of buried bit lines is separated by an oxide layer from the semiconductor substrate.

42. The electronic system of claim 36, wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

43. An electronic system, comprising:

a processor; and

a memory device including an array of memory cells coupled to the processor, wherein the array of memory cells includes;

a number of pillars extending outwardly from a semiconductor substrate, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;

a pair of single crystalline vertical transistors formed along opposing sides of each pillar, wherein each single crystalline vertical transistor includes;

an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;

an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;

an ultra thin single crystalline vertical body region formed along side of the oxide layer and which couples the first and the second source/drain regions;

a floating gate opposing the vertical body region and separated therefrom by a floating gate oxide;

wherein a horizontal junction depth for the first and the second ultra thin single crystalline vertical source/drain regions is much less than a vertical length of the ultra thin single crystalline vertical body region;

a plurality of buried bit lines formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells;

a plurality of control lines separated from each floating gate by an insulator layer; and

a plurality of data lines coupled to the second contact layer in row adjacent pillars.

44. The electronic system of claim 43, wherein each floating gate is formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the ultra thin single crystalline vertical body regions in column adjacent pillars on opposing sides of the trench, and wherein the pair of floating gates are separated by an insulator layer.

45. The electronic system of claim 44, wherein the plurality of control lines are formed in the trench below the top surface of the pillar and between the pair of floating gates, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

46. The electronic system of claim 44, wherein the plurality of control lines are disposed vertically above the floating gates.

47. The electronic system of claim 43, wherein each floating gate includes a horizontally oriented floating gate having a vertical side of less than 100 nanometers, and wherein the horizontally oriented floating gate is separated by a floating gate oxide from the ultra thin single crystalline vertical body regions on opposing sides of the trench for column adjacent pillars.

48. The electronic system of claim 43, wherein the plurality of control lines are disposed vertically above the floating gates.

49. The electronic system of claim 43, wherein each single crystalline vertical transistor has a vertical length of less than 100 nanometers and a horizontal width of less than 10 nanometers.