Shallow trench isolation chemical-mechanical polishing process

• US 6,424,019 B1
• Filed: 02/18/2000
• Issued: 07/23/2002
• Est. Priority Date: 06/16/1998
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Hsia, Shouli Steve, Pallinti, Jayanthi, Wang, Yanhua
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US09/507,042
• Time in Patent Office: 886 Days
• Field of Search: 257/752, 257/499, 257/500, 257/501, 257/506, 438/691, 438/692, 438/700
• US Class Current: 257/499
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Abstract

A process for fabricating a trench filled with an insulating material in a surface of an integrated circuit substrate is described. One step of the process includes defining a masking layer on a composite layered stack above a region to be protected on the integrated circuit substrate surface. The composite layered stack includes a layer of a first material and a polishing stopping layer. The layer of the first material has a polishing rate by chemical mechanical polishing that is greater than a polishing rate by chemical mechanical polishing of the insulating material. Another step of the process includes etching through the composite layered stack and the integrated circuit substrate to form the trench in the integrated circuit substrate surface and depositing the insulating material on the integrated circuit substrate surface such that the trench is filled with the insulating material. A yet another step of the process includes polishing the integrated circuit substrate surface to remove a substantial portion of the composite layered stack and a portion of the insulating material adjacent to the composite layered stack at about a same rate. The polishing step facilitates in forming a substantially planar surface of the insulating material above the trench and reducing a likelihood of forming of a concave region near a middle region of the surface of the insulating material. The concave region recesses inwardly into the surface of the insulating material in the trench.

Claims

1. A semiconductor wafer wherein trenches are formed in predefined areas, the trenches providing electrical isolation between adjacent active devices formed on the semiconductor wafer, the predefined areas comprising:

a semiconductor substrate;

a native oxide layer deposited on the substrate;

a first polish stop layer deposited on the native oxide layer;

a soft material layer deposited on the first polish stop layer and through which trenches are etched in the predefined areas, the trenches extending through the soft material layer, the first polish stop layer, the native oxide layer and a predefined portion of the semiconductor substrate;

an insulating layer deposited on the soft material layer, which insulating layer fills the trenches, wherein the rate of removal of the soft material layer under chemical-mechanical polishing is between 50% to 200% greater than the rate of removal of the insulating layer under chemical-mechanical polishing and the thickness of the soft material layer is between 1 to 10 times the thickness of the polish stop layer and the polish stop layer has a thickness between approximately 2,000 and approximately 20,000 angstroms.

2. The semiconductor wafer of claim 1 wherein the soft material layer includes at least one material selected from the group consisting of tungsten, doped silicon dioxide and polymer.

3. The semiconductor wafer of claim 1 wherein the first polish stop layer comprises at least one of silicon nitride and silicon oxynitride.

4. The semiconductor wafer of claim 1 wherein the insulating layer comprises silicon dioxide.