Phase lock loop (PLL) apparatus and method
First Claim
1. A circuit, comprising:
- a clock generator that generates a plurality of first clock signals having different phases, each first clock signal having a first frequency that is less than a reference frequency; and
a prescaler coupled to the clock generator that receives the plurality of first clock signals to generate a second clock signal based on the reference frequency that is higher than the first frequency, wherein the prescaler comprises, a divider circuit coupled to receive one of the plurality of first clock signals, a sampler circuit that receives an output signal of the divider circuits, wherein the sampler circuit outputs a plurality of third clock signals, a multiplexer coupled to receive the third plurality of clock signals and a selection signal, wherein the multiplexer outputs the second clock signal, and a counter circuit coupled between the divider circuit and the multiplexer.
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Abstract
A phase lock loop (PLL) and methods for using same is provided that includes a multiple-feedback CMOS voltage control oscillator (VCO) and multi-phase sampling fractional-N prescaler. The PLL provides increased performance characteristics for a single chip CMOS radio frequency (RF) communications system. The multiple feedback CMOS VCO maintains an amplitude of a VCO signal while reducing a rise/fall time of the VCO signal. The multiple feedback CMOS VCO further reduces supply noise effects. The multi-phase sampling fractional-N prescaler provides sufficient bandwidth for a CMOS VCO while maintaining spectral purity and reducing fractional-spur. The multi-phase sampling fractional-N prescaler can include a divider, a sampler circuit, a selector circuit and a modular counter.
92 Citations
24 Claims
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1. A circuit, comprising:
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a clock generator that generates a plurality of first clock signals having different phases, each first clock signal having a first frequency that is less than a reference frequency; and
a prescaler coupled to the clock generator that receives the plurality of first clock signals to generate a second clock signal based on the reference frequency that is higher than the first frequency, wherein the prescaler comprises, a divider circuit coupled to receive one of the plurality of first clock signals, a sampler circuit that receives an output signal of the divider circuits, wherein the sampler circuit outputs a plurality of third clock signals, a multiplexer coupled to receive the third plurality of clock signals and a selection signal, wherein the multiplexer outputs the second clock signal, and a counter circuit coupled between the divider circuit and the multiplexer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
a first pair of transistors coupled in series by second electrodes between a first node and a first prescribed voltage, wherein control electrodes of the first pair of transistors are respectively coupled to the fourth and third input terminals;
a second pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein control electrodes of the second pair of transistors are respectively coupled to the first and second input terminals;
a third pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein control electrodes of the third pair of transistors are respectively coupled to fourth and third input terminals, and wherein the commonly coupled second electrodes are coupled to the first output terminal;
a fourth pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein control electrodes of the fourth pair of transistors are respectively coupled to the first input terminal and the second input terminal, and wherein the second electrode of the fourth pair of transistors are coupled to the second output terminal;
a feedback circuit coupled between a second node and a third node;
a fifth pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein the second electrodes of the fifth pair of transistors are coupled to the first output terminal, and wherein control electrodes of the fifth pair of transistors are coupled to the third node;
a sixth pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein the second electrodes of the sixth pair of transistors are coupled to the second output terminal, and wherein control electrodes of the sixth pair of transistors are coupled to the second node;
a seventh transistor coupled between a first node and a first output terminal having a control electrode coupled to the second output terminal;
an eighth transistor coupled between a first node and the second output terminal, wherein the eighth transistor has a control electrode coupled to the first output terminal; and
a ninth transistor coupled between a second prescribed voltage and the first node.
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5. The circuit of claim 4, wherein the feedback circuit includes a feedback transistor coupled to receive a feedback control signal.
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6. The circuit of claim 1, wherein the divider circuit comprises a pulse-swallow divider circuit, and wherein the sampler circuit comprises a plurality of flip flops coupled in series, wherein each of the plurality of flip flops receives a corresponding one of the first plurality of clock signals and outputs one of the third plurality of clock signals, and wherein a first flip flop receives the output signal of the divider circuit.
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7. The circuit of claim 1, further comprising:
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a phase detector that receives the second clock signal and a reference clock signal;
a charge pump circuit coupled to the phase detector; and
a loop filter coupled to the charge pump that outputs the feedback control signal to the clock generator.
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8. The circuit of claim 7, wherein the clock generator is a voltage controlled oscillator (VCO), and the second clock signal is a divided clock signal.
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9. The circuit of claim 8, wherein the circuit is a CMOS circuit formed on a single chip.
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10. The circuit of claim 8, wherein the prescaler reduces a fractional spur in phase noise generated by the VCO.
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11. A receiver for a radio frequency (RF) communications system, comprising:
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an RF section coupled to receive an input RF signal;
a baseband section coupled to the RF section to receive corresponding baseband signals from the RF section;
a phase lock loop (PLL) coupled to the RF section, wherein the phase lock loop comprises, a phase detector that receives a reference frequency signal, a charge pump and loop filter coupled to the phase detector, a VCO that generates a plurality of first clock signals having different phases, each first clock signal having a first frequency that is less than a reference frequency of the reference frequency signal, and a prescaler coupled to said VCO for receiving the plurality of first clock signals to transmit a divided clock signal to the phase detector, wherein the prescaler comprises, a divider circuit coupled to receive one of the plurality of first clock signals, a sampler circuit that receives an output signal of the divider circuits, wherein the sampler circuit outputs a plurality of third clock signals, a multiplexer coupled to receive the third plurality of clock signals and a selection signal, wherein the multiplexer outputs the second clock signal, and a counter circuit coupled between the divider circuit and the multiplexer; and
a tuning circuit that outputs a control signal to the baseband section. - View Dependent Claims (12, 13, 14)
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15. A circuit, comprising:
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a clock generator that generates a plurality of first clock signals having different phases, each first clock signal having a first frequency that is less than a reference frequency; and
a prescaler coupled to the clock generator that receives the plurality of first clock signals to generate a second clock signal based on the reference frequency that is higher than the first frequency, wherein the clock generator includes a plurality of delay cells coupled in series for providing the plurality of first clock signals having different phases, wherein a first one of the plurality of delay cells receive feedback signals from subsequent ones of the delay cells, wherein each of the delay cells includes first and second output terminals and first through fourth input terminals, and wherein one of the delay cells comprises, a first pair of transistors coupled in series by second electrodes between a first node and a first prescribed voltage, wherein control electrodes of the first pair of transistors are respectively coupled to the fourth and third input terminals, a second pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein control electrodes of the second pair of transistors are respectively coupled to the first and second input terminals, a third pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein control electrodes of the third pair of transistors are respectively coupled to fourth and third input terminals, and wherein the commonly coupled second electrodes are coupled to the first output terminal, a fourth pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein control electrodes of the fourth pair of transistors are respectively coupled to the first input terminal and the second input terminal, and wherein the second electrode of the fourth pair of transistors are coupled to the second output terminal, a feedback circuit coupled between a second node and a third node, a fifth pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein the second electrodes of the fifth pair of transistors are coupled to the first output terminal, and wherein control electrodes of the fifth pair of transistors are coupled to the third node, a sixth pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein the second electrodes of the sixth pair of transistors are coupled to the second output terminal, and wherein control electrodes of the sixth pair of transistors are coupled to the second node, a seventh transistor coupled between a first node and a first output terminal having a control electrode coupled to the second output terminal, an eighth transistor coupled between a first node and the second output terminal, wherein the eighth transistor has a control electrode coupled to the first output terminal, and a ninth transistor coupled between a second prescribed voltage and the first node.
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16. A clock generating circuit, comprising:
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a clock generator that generates a plurality of first clock signals having different phases, each first clock signal having a first frequency that is less than a reference frequency, wherein the clock generator includes a plurality of delay cells coupled in series for providing the plurality of first clock signals having different phases, wherein a first one of the plurality of delay cells receive feedback signals from subsequent ones of the delay cells, and wherein each of the delay cells comprises, first and second output terminals and first through fourth input terminals, a noise rejection circuit connected between a second prescribed voltage and a first node, a first circuit connected between the first node, a first prescribed reference voltage, the four input terminals and the two output terminals, wherein the first circuit receives first through fourth input signals to generate first and second output signals, a first feedback circuit connected between the first node, the first and second output terminals and the first through fourth input terminals to reduce rise and fall time intervals of the first and second output signals, and a second feedback circuit connected between the first node and the first and second output terminals, wherein the second feedback circuit receives a control voltage that controls a frequency of the clock generating circuit. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
the first pair of transistors coupled in series by second electrodes between a first node and a first prescribed voltage, wherein control electrodes of the first pair of transistors are respectively coupled to the fourth and third input terminals, and a second pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein control electrodes of the second pair of transistors are respectively coupled to the first and second input terminals.
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19. The clock generator of claim 16, wherein the second feedback circuit comprises:
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a first transistor coupled between a first node and a first output terminal having a control electrode coupled to the second output terminal, and a second transistor coupled between a first node and the second output terminal, wherein the second transistor has a control electrode coupled to the first output terminal.
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20. The clock generator of claim 16, wherein the first feedback circuit comprises:
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a third pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein control electrodes of the third pair of transistors are respectively coupled to fourth and third input terminals, and wherein the commonly coupled second electrodes are coupled to the first output terminal;
a fourth pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein control electrodes of the fourth pair of transistors are respectively coupled to the first input terminal and the second input terminal, and wherein the second electrode of the fourth pair of transistors are coupled to the second output terminal;
a control circuit coupled between a second node and a third node;
a fifth pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein the second electrodes of the fifth pair of transistors are coupled to the first output terminal, and wherein control electrodes of the fifth pair of transistors are coupled to the third node; and
a sixth pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein the second electrodes of the sixth pair of transistors are coupled to the second output terminal, and wherein control electrodes of the sixth pair of transistors are coupled to the second node.
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21. The clock generator of claim 20, wherein the second feedback circuit comprises:
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a first transistor coupled between a first node and a first output terminal having a control electrode coupled to the second output terminal; and
a second transistor coupled between a first node and the second output terminal, wherein the second transistor has a control electrode coupled to the first output terminal.
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22. The clock generator of claim 21, wherein the first circuit comprises:
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the first pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein control electrodes of the first pair of transistors are respectively coupled to the fourth and third input terminals; and
a second pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein control electrodes of the second pair of transistors are respectively coupled to the first and second input terminals.
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23. The clock generator of claim 22, wherein the noise rejection circuit comprises a transistor coupled between a second prescribed voltage and the first node.
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24. A delay cell, comprising:
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a first pair of transistors coupled in series by second electrodes between a first node and a first prescribed voltage, wherein control electrodes of the first pair of transistors are respectively coupled to the fourth and third input terminals;
a second pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein control electrodes of the second pair of transistors are respectively coupled to the first and second input terminals;
a third pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein control electrodes of the third pair of transistors are respectively coupled to fourth and third input terminals, and wherein the commonly coupled second electrodes are coupled to the first output terminal;
a fourth pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein control electrodes of the fourth pair of transistors are respectively coupled to the first input terminal and the second input terminal, and wherein the second electrode of the fourth pair of transistors are coupled to the second output terminal;
a feedback circuit coupled between a second node and a third node;
a fifth pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein the second electrodes of the fifth pair of transistors are coupled to the first output terminal, and wherein control electrodes of the fifth pair of transistors are coupled to the third node;
a sixth pair of transistors coupled in series by second electrodes between the first node and the first prescribed voltage, wherein the second electrodes of the sixth pair of transistors are coupled to the second output terminal, and wherein control electrodes of the sixth pair of transistors are coupled to the second node;
a seventh transistor coupled between a first node and a first output terminal having a control electrode coupled to the second output terminal;
an eighth transistor coupled between a first node and the second output terminal, wherein the eighth transistor has a control electrode coupled to the first output terminal; and
a ninth transistor coupled between a second prescribed voltage and the first node.
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Specification