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Phase lock loop (PLL) apparatus and method

  • US 6,424,192 B1
  • Filed: 11/13/2000
  • Issued: 07/23/2002
  • Est. Priority Date: 07/24/1998
  • Status: Expired due to Term
First Claim
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1. A circuit, comprising:

  • a clock generator that generates a plurality of first clock signals having different phases, each first clock signal having a first frequency that is less than a reference frequency; and

    a prescaler coupled to the clock generator that receives the plurality of first clock signals to generate a second clock signal based on the reference frequency that is higher than the first frequency, wherein the prescaler comprises, a divider circuit coupled to receive one of the plurality of first clock signals, a sampler circuit that receives an output signal of the divider circuits, wherein the sampler circuit outputs a plurality of third clock signals, a multiplexer coupled to receive the third plurality of clock signals and a selection signal, wherein the multiplexer outputs the second clock signal, and a counter circuit coupled between the divider circuit and the multiplexer.

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