Multi-layer switching apparatus and method

• US 6,424,659 B2
• Filed: 07/17/1998
• Issued: 07/23/2002
• Est. Priority Date: 07/17/1998
• Status: Expired due to Term

• Current Assignee: Sonus Networks Incorporated (Ribbon Communications, Inc.)
• Original Assignee: Network Equipment Technologies Incorporated (Ribbon Communications, Inc.)
• Inventors: Viswanadham, Krishna, Veerina, Mahesh
• Primary Examiner(s): Hsu, Alpus H.
• Assistant Examiner(s): NGUYEN, BRIAN D
• Application Number:
  US09/118,458
• Publication Number:
  US 20010043614A1
• Time in Patent Office: 1,467 Days
• Field of Search: 370/469, 370/463, 370/395, 370/396, 370/397, 370/412, 370/413, 370/414, 370/415, 370/416, 370/417, 370/418, 370/419, 370/359, 370/392, 370/229, 370/230, 370/465, 370/471, 370/428, 370/389
• US Class Current: 370/469
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/602 Multilayer or multiprotocol switching, e.g. IP switching

Abstract

Multilayer switching device and associated technique enables simultaneous wire-speed routing at OSI layer 3, wire-speed switching at layer 2, and support multiple interfaces at layer 1. Implementation may be embodied using one or more integrated circuits (ASIC), RISC processor, and software, thereby providing wire-speed performance on interfaces, in various operational modes.

Claims

1. A multi-level packet switching system comprising:

at least two first-level switches for packet reception or transmission, each first level switch comprising an integrated switch module that enables multi-layer switching and a processing module coupled to the integrated switch module; and

a second-level switch comprising a cross-bar switch coupled to a multi-protocol router, said second level switch also coupled to each of the first-level switches for enabling packet communication between the second-level switch and the first-level switches;

wherein;

each of said first and second-level switches are configured to determine which of Layer-2 switching and Layer-3 routing needs to be performed based on a Layer-2 lookup of packets received by the switching system and then perform wire-speed routing at Layer-3 and wire-speed switching at Layer-2 according to the Layer-2 lookup;

said wire-speed routing and said wire-speed switching are performed at the same time;

said integrated switch module comprises,

a receive block configured to receive packets from a network communication medium;

a content addressable memory (CAM) containing Layer-2 routing information;

a CAM interface coupled to said receive block and configured to,

retrieve header address information from packets received by said receive block,

lookup Layer-2 information stored in said CAM based on the retrieved header address information, and

identify whether the packet associated with the retrieved header address information requires Layer-2 switching or Layer-3 routing based on the Layer-2 information;

a forwarding engine, coupled to said CAM interface and said receive block, configured to direct each of said Layer-3 routing and Layer-2 switching to be performed on the received packets based on said identification;

said processing module includes programming for CAM header processing that assists in source lookup, source port read, and source learning; and

said source learning comprises a process for learning Media Access Control (MAC) addresses and parts of data packets arriving from Ethernet ports coupled to the corresponding first level switch and applying the learned addresses and parts in said source lookup and said source port read.

2. The multi-level packet switching system according to claim 1, wherein:

said multi-level packet switching system is embodied on at least one Application Specific Integrated Circuit (ASIC) including a Reduced Instruction Set Computer (RISC) processor and software that enables said Layer-2 switching, and Layer-3 routing, and Layer-2 lookup of received packets;

said multi-level packet switching apparatus includes a memory module that stores said software; and

said RISC processor and software comprising said processing module.

3. The multi-level packet switching system according to claim 2, further comprising:

a Layer-2 module comprising said Layer-2 lookup and said integrated switch module, said Reduced Instruction Set Computer (RISC) processor, and said software configured to effectively enable Layer-2 packet switching;

a Layer-3 module comprising said Layer-3 lookup module, said integrated switch module, said RISC processor, and said software configured to effectively enable Layer-3 packet routing; and

a data path module;

wherein said Layer-2 lookup determines Layer-2 switching and Layer-3 routing to be performed on packets received by said system; and

said Layer-2 module and said Layer-3 module respectively perform processing required for each of Layer-2 switching and Layer-3 routing independently and in parallel based on said Layer-2 lookup.

4. The multi-level packet switching system of claim 3, wherein:

said forwarding engine configured to direct one of Layer-2 switching and Layer-3 routing of packets received by said system based on the Layer-2 lookup of each packet.

5. The multi-level packet switching system of claim 3 wherein the Layer-3 module includes:

a hash look-up module for accessing a hash table containing Layer-3 routing information.

6. The multi-level packet switching system of claim 5 wherein the hash look-up module further modifies a packet received by said multi-level packet switching system.

7. The multi-level packet switching system of claim 5 wherein the hash look-up module further modifies an age flag in an aging table.

8. The multi-level packet switching system of claim 5 wherein the hash look-up module further manages a packet queue.

9. The multi-level packet switching system of claim 5 wherein the hash look-up module further processes packet attributes.

10. The multi-level packet switching system of claim 3 wherein the datapath module comprises:

a set of pipeline buffers coupled to said Reduced Instruction Set Computer (RISC) processor and configured to receive write data from the RISC processor;

a state machine configured to coordinate operation of the pipeline buffers, including a buffer scheduler module for scheduling the pipeline buffers.

11. The multi-level packet switching system of claim 10 wherein the memory module includes a Direct Memory Access (DMA) module for effectively enabling DMA access to the memory module.

12. The multi-level packet switching system of claim 2 wherein the memory module comprises:

a local memory, a control memory, a cache memory, or a packet memory.

13. The multi-level packet switching system according to claim 2, wherein:

said Application Specific Integrated Circuit (ASIC) includes said at least two first-level switches, and said second-level switch; and

each of said first level switches include,

a Reduced Instruction Set Computer (RISC) processor interface coupled to said RISC processor,

said forwarding engine coupled to said receive block which comprises a LAN Bus receiving device,

said CAM interface further coupled to said RISC Processor,

a layer 3 lookup module coupled to the RISC processor and said forwarding engine, and

a Q management and scheduler, coupled to said RISC processor and a LAN Bus transmit device, and configured to transmit received packets according to the Layer-2 and Layer-3 operations performed by said multi-level packet switching apparatus.

14. The multi-level packet switching system according to claim 13, wherein said Reduced Instruction Set Computer (RISC) processor is at least a 32-bit Million Instructions Per Second (MIPS) RISC processor having a multiplexed bus.

15. The multi-level packet switching system of claim 1 wherein the integrated switch module comprises:

an integrated single-chip circuit for effectively enabling packet traffic broadcasting.

16. The multi-level packet switching system of claim 1 wherein:

said first-level switch is coupled to at least one hub.

17. The multi-level packet switching system according to claim 1, wherein said Layer-2 switching and said Layer-3 routing are performed simultaneously at wire-speed.